Bhagirath Narahari

Strong minimum energy topology in wireless sensor networks: NP-completeness and heuristics

Wireless sensor networks have recently attracted lots of research effort due to the wide range of applications. These networks must operate for months or years. However, the sensors are powered by battery, which may not be able to be recharged after they are deployed. Thus, energy-aware network management is extremely important. In this paper, we study the following problem: Given a set of sensors in the plane, assign transmit power to each sensor such that the induced topology containing only bidirectional links is strongly connected. This problem is significant in both theory and application. We prove its NP-completeness and propose two heuristics: power assignment based on minimum spanning tree (denoted by MST) and incremental power. We also show that the MST heuristic has a performance ratio of 2. Simulation study indicates that the performance of these two heuristics does not differ very much, but; on average, the incremental power heuristic is always better than MST.

SAFE-OPS: An approach to embedded software security

The new-found ubiquity of embedded processors in consumer and industrial applications brings with it an intensified focus on security, as a strong level of trust in the system software is crucial to their widespread deployment. The growing area of software protection attempts to address the key steps used by hackers in attacking a software system. In this paper, we introduce a unique approach to embedded software protection that utilizes a hardware/software codesign methodology. Results demonstrate that this framework can be the successful basis for the development of embedded applications that meet a wide range of security and performance requirements.

The banyan-hypercube networks

The authors introduce a family of networks that are a synthesis of banyans and hypercubes and are called the banyan-hypercubes (BH). They combine the advantageous features of banyans and hypercubes and thus have better communication capabilities. The networks can be viewed as consisting of interconnecting hypercubes. It is shown that many hypercube features can be incorporated into BHs with regard to routing, embedding of rings and meshes, and partitioning, and that improvements over the hypercube result are made. In particular, it is shown that BHs have better diameters and average distances than hypercubes, and they embed pyramids and multiple pyramids with dilation cost 1. An optimal routing algorithm for BHs and an efficient partitioning strategy are presented. >

OS support for detecting Trojan circuit attacks

Rapid advances in integrated circuit (IC) development predicted by Moores Law lead to increasingly complex, hard to verify IC designs. Design insiders or adversaries employed at untrusted locations can insert malicious Trojan circuits capable of launching attacks in hardware or supporting software-based attacks. In this paper, we provide a method for detecting Trojan circuit denial-of-service attacks using a simple, verifiable hardware guard external to the complex CPU. The operating system produces liveness checks, embedded in the software clock, to which the guard can respond. We also present a novel method for the OS to detect a hardware-software (HW/SW) Trojan privilege escalation attack by using OS-generated checks to test if the CPU hardware is enforcing memory protection (MP). Our implementation of fine-grained periodic checking of MP enforcement incurs only 2.2% overhead using SPECint 2006.

Transform-based indexing of audio data for multimedia databases

Since the relative proportion of multimedia (video, image and audio) data within databases is expected to increase substantially in the future, keyword-based indexing would be inadequate and efficient content-based query and retrieval are required. The problem of devising content based query, indexing, and retrieval for these newer data types remains an open and challenging problem. While considerable attention has recently been given to image (and, to some extent, video) indexing, much less has been devoted to the problem of indexing its unidimensional counterpart-audio data. The paper proposes content-based indexing schemes for audio data in multimedia databases. The methods are based on transform techniques used in signal processing which transform data from time (or spatial) domain to frequency domain. This offers many advantages such as easy removal of noise, efficient compression and different types of processing. Two algorithms for indexing are presented along with experimental results.

Providing secure execution environments with a last line of defense against Trojan circuit attacks

Integrated circuits (ICs) are often produced in foundries that lack effective security controls. In these foundries, sophisticated attackers are able to insert malicious Trojan circuits that are easily hidden in the large, complex circuitry that comprises modern ICs. These so-called Trojan circuits are capable of launching attacks directly in hardware, or, more deviously, can facilitate software attacks. Current defense against Trojan circuits consists of statistical detection techniques to find such circuits before product deployment. The fact that statistical detection can result in false negatives raises the obvious questions: can attacks be detected post-deployment, and is secure execution nonetheless possible using chips with undetected Trojan circuits? In this paper we present the Secure Heartbeat And Dual-Encryption (SHADE) architecture, a compiler-hardware solution for detecting and preventing a subset of Trojan circuit attacks in deployed systems. Two layers of hardware encryption are combined with a heartbeat of off-chip accesses to provide a secure execution environment using untrusted hardware. The SHADE system is designed to complement pre-deployment detection techniques and to add a final, last-chance layer of security.

CODESSEAL: Compiler/FPGA approach to secure applications

The science of security informatics has become a rapidly growing field involving different branches of computer science and information technologies. Software protection, particularly for security applications, has become an important area in computer security. This paper proposes a joint compiler/hardware infrastructure – CODESSEAL – for software protection for fully encrypted execution in which both program and data are in encrypted form in memory. The processor is supplemented with an FPGA-based secure hardware component that is capable of fast encryption and decryption, and performs code integrity verification, authentication, and provides protection of the execution control flow. This paper outlines the CODESSEAL approach, the architecture, and presents preliminary performance results.

An efficient heuristic scheme for dynamic remapping of parallel computations

Abstract In applications where a sequence of different tasks is to be performed, the computational load of a task varies dynamically and can become severely imbalanced between successive tasks. These dynamic changes in the load suggest that a remapping of the load must be performed before the next task in the sequence is executed. A remapping scheme must: (1) estimate load measures for each task and dynamically compute load distribution, then (2) compute a remapping and (3) remap the load according to the mapping generation in (2). This paper presents an experimental analysis of a heuristic remapping scheme applied to a motion estimation system in computer vision, and implemented on an Intel iPSC/2 machine. We discuss a fast heuristic mapping algorithm to compute the remapping that compares favorably with the slower optimal algorithm. Our experiments show that the heuristic remapping scheme results in significant performance gains, of over 3 times improvement in speedup, while incurring low overheads.

High-Performance Software Protection Using Reconfigurable Architectures

One of the key problems facing the computer industry today is ensuring the integrity of end-user applications and data. Researchers in the relatively new field of software protection investigate the development and evaluation of controls that prevent the unauthorized modification or use of system software. While many previously developed protection schemes have provided a strong level of security, their overall effectiveness has been hindered by a lack of transparency to the user in terms of performance overhead. Other approaches take to the opposite extreme and sacrifice security for the sake of this transparency. In this work we present an architecture for software protection that provides for a high level of both security and user transparency by utilizing field programmable gate array (FPGA) technology as the main protection mechanism. We demonstrate that by relying on FPGA technology, this approach can accelerate the execution of programs in a cryptographic environment, while maintaining the flexibility through reprogramming to carry out any compiler-driven protections that may be application-specific.

Mapping a chain task to chained processors

Abstract We present algorithms for computing an optimal mapping of a chain task to chained processors. Our algorithm has time complexity no larger than O( m + p 1+ e ) for any small e>0. This represents an improvement over the recent best results of an O( mp ) algorithm and an O( m + p 2 log 2 m ) algorithm. We extend our algorithm to the case of mapping a ring task to a ring of processors with time complexity O( m 1+ e ) and the case of mapping multiple chain tasks to chained processors with time complexity O( mn + p 1+ e ).