Bharath K Vasan

Soft Elastomeric Capacitor Network for Strain Sensing Over Large Surfaces

Field applications of existing sensing solutions to structural health monitoring (SHM) of civil structures are limited. This is due to economical and/or technical challenges in deploying existing sensing solutions to monitor geometrically large systems. To realize the full potential of SHM solutions, it is imperative to develop scalable cost-effective sensing strategies. We present a novel sensor network specifically designed for strain sensing over large surfaces. The network consists of soft elastomeric capacitors (SECs) deployed in an array form. Each SEC acts as a surface strain gage transducing local strain into changes in capacitance. Results show that the sensor network can track strain history above levels of 25 με using an inexpensive off-the-shelf data acquisition system. Tests at large strains show that the sensors sensitivity is almost linear over strain levels of 0-20%. We demonstrate that it is possible to reconstruct deflection shapes for a simply supported beam subjected to quasi-static loads, with accuracy comparable to resistive strain gages.

Low-Distortion Sine Wave Generation Using a Novel Harmonic Cancellation Technique

A novel technique is proposed to generate robust, low distortion sine waves. In this method, outputs of a phase shift oscillator (PSO) are weighted and summed to obtain multiple outputs with very low distortion and precise phase relationship. The method allows a programmable number of harmonic distortion components to be cancelled over a wide frequency range. This work derives the condition for the weights on the outputs of the PSO to be a real quantity, and demonstrates how this can be used to generate low distortion sine waves. With the proposed method, in an N-stage PSO, harmonics up to N-2th can be canceled. Simulation results using commercial operational amplifier spice models are presented to demonstrate low distortion sine wave generation over 2 kHz-180 kHz frequency range. The method has been experimentally verified using extremely low-cost, discrete components to produce 100 dB total harmonic distortion (THD) sine wave.

Signal generators for cost effective BIST of ADCs

Conventional approach to linearity testing of ADCs requires a signal generator that is more linear than the device under test (DUT). Recently introduced ADC testing algorithms dramatically relax the linearity requirements on the signal generator in exchange for maintaining a known functional relationship between two unknown nonlinear test signals. Simple signal generators that can be used to generate the two non-linear signals are discussed. Simulation results show that the generated signals can be used to test ADCs with resolution ranging between 6 and 17bits.

Sinusoidal signal generation for production testing and BIST applications

A novel technique to generate spectrally pure sinusoidal signals is proposed. The technique provides a dramatic improvement in spectral performance compared to the existing state of the art. With the proposed approach, spectral performance is inherently robust to variation in operating frequency and spectral characterization is programmable over frequencies. A circuit using extremely low cost operational amplifiers and 5 % accurate passive components has been built that can generate a sine wave with THD of lesser than -100dB at frequency, f=2.737 KHz .

Linearity testing of ADCs using low linearity stimulus and Kalman filtering

Traditional linearity testing of ADCs involves using a spectrally pure or a highly linear stimulus, along with a large number of samples per code to average out the effects of noise. Test equipments need to house expensive instruments to provide the highly linear stimulus. The large number of samples required for the procedure results in long test times. These two factors are prime contributors to the test cost. In this paper, algorithms which use low linearity stimuli and a Kalman Filter to reduce both the hardware resources and the test time for the test procedure have been proposed. Simulations results for a 14-bit ADC show that a 7-bit linear stimulus with one sample per code can be used to measure the INL of the ADC with a maximum estimation error of 1 LSB.

Stimulus generator for SEIR method based ADC BIST

Testing of ADC in SOC is a significant challenge since it usually has no connection to the outside. Built-in self-test (BIST) is regarded as a promising alternative to traditional test. Most reported ADC BIST research works try to replicate a production test scheme on chip. This approach requires input ramp with high linearity which is hard to achieve on chip. This paper investigates signal generator implementation issues of adapting stimulus error identification and removal method which was presented for production test into a practical ADC BIST solution. A stimulus generator using very small transistor count is presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that generated signals with less than 7 bits linearity, together with the simple level shifts, are able to test a 16-bit ADC to 16 bit accuracy level. These results demonstrate that accurate BIST of deeply embedded AMS blocks may be practically implemented on chip with very low overhead.

On Chip Signal Generators for Low Overhead ADC BIST

Testing of ADCs deeply embedded in SOCs is a significant challenge due to access limitations. ADC Built-in self-test (BIST) is considered a promising alternative to traditional test. This paper investigates implementation issues in adapting the stimulus error identification and removal (SEIR) algorithm, originally developed for production test, into a practical ADC BIST solution. Signal generators with very low transistor count and area consumption are presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that the generated signals, together with the level shifts, are able to test a 16-bit ADC to 16 bit accuracy levels. These results demonstrate that accurate BIST of deeply embedded analog and mixed-signal (AMS) blocks may be practically implemented on chip with very low overhead.

ADC integral non-linearity testing with low linearity monotonic signals

Methods to test the Integral Non-Linearity (INL) of Analog-to-Digital Converters (ADCs) using any monotonic signal with low linearity are proposed. Two methods that estimate the INL of the ADC by removing the error due to non-linearity in the stimulus are described. Signals with linearity dramatically lesser than the ADC under test, can be used to accurately estimate the INL of the ADC. Simulation results show that the maximum INL estimation error for testing 14-bit ADCs using 36 dB pure sinusoids and 7-bit linear exponential signals is under 0.6 LSB.

Linearity testing of Analog-to-Digital Converters using imprecise sinusoidal excitations

One of the biggest challenges associated with testing the linearity of high performance Analog-to-Digital Converters (ADCs) is generating a test stimulus more linear or spectrally more pure than the device under test. In this paper we propose algorithms that allow easy to generate, imprecise sinusoidal excitations that differ by a constant voltage to characterize the Integral nonlinearity (INL) of high resolution ADCs. Simulation results indicate that sine waves with SFDR<40dB can be used to accurately identify the INL of 16-bit ADCs with the proposed methods.