Bharathwaj Muthuswamy

Implementing Memristor Based Chaotic Circuits

This paper provides a practical implementation of a memristor based chaotic circuit. We realize a memristor using off-the-shelf components and then construct the memristor along with the associated chaotic circuit on a breadboard. The goal is to construct a physical chaotic circuit that employs the four fundamental circuit elements — the resistor, capacitor, inductor and the memristor. The central concept behind the memristor circuit is to use an analog integrator to obtain the electric flux across the memristor and then use the flux to obtain the memristors characterstic function.

SIMPLEST CHAOTIC CIRCUIT

A chaotic attractor has been observed with an autonomous circuit that uses only two energy-storage elements: a linear passive inductor and a linear passive capacitor. The other element is a nonlinear active memristor. Hence, the circuit has only three circuit elements in series. We discuss this circuit topology, show several attractors and illustrate local activity via the memristors DC vM - iM characteristic.

Memristor-Based Chaotic Circuits

Abstract Ever since its physical fabrication in 2008, the memristor has been promising in the fields of nanoelectronics, computer logic and neuromorphic computers. Taking advantage of the circuit properties of the memristor, this paper proposes memristor-based chaotic circuits. For the first time, memristor-based chaotic circuits have been derived from the canonical Chua’s circuit. These circuits present opportunities for developing applications under the constraints of scalability and low power. They also provide a memristor-based framework for secure communications with chaos.

A Generic Model of Memristors With Parasitic Components

In this paper, a generic model of memristive systems, which can emulate the behavior of real memristive devices is proposed. Non-ideal pinched hysteresis loops are sometimes observed in real memristive devices. For example, the hysteresis loops may deviate from the origin over a broad range of amplitude A and frequency f of the input signal. This deviation from the ideal case is often caused by parasitic circuit elements exhibited by real memristive devices. In this paper, we propose a generic memristive circuit model by adding four parasitic circuit elements, namely, a small capacitance, a small inductance, a small DC current source, and a small DC voltage source, to the memristive device. The adequacy of this model is verified experimentally and numerically with two thermistors (NTC and PTC) memristors.

A Route to Chaos Using FPGAs

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A mixed-signal EEG interface circuit for use in first year electronics courses

price are net prices, subject to local VAT. Prices indicated with * include VAT for books; the €(D) includes 7% for Germany, the €(A) includes 10% for Austria. Prices indicated with ** include VAT for electronic products; 19% for Germany, 20% for Austria. All prices exclusive of carriage charges. Prices and other details are subject to change without notice. All errors and omissions excepted. B. Muthuswamy, S. Banerjee A Route to Chaos Using FPGAs

OPTIMAL CNN TEMPLATES FOR LINEARLY-SEPARABLE ONE-DIMENSIONAL CELLULAR AUTOMATA

In their first electronics course, many students find operational amplifiers, analog filters and sensor interface circuitry perplexing and daunting. The purpose of this paper is to present a circuit that addresses these pitfalls. A simplified electroencephelogram (EEG) circuit that is interfaced to a digital backend is proposed. The completed circuit involves using instrumentation amplifiers and filters for the EEG interface. The digital backend helps analyze EEG data on the computer.

Two Element Chaotic and Hyperchaotic Circuits

In this tutorial, we present optimal Cellular Nonlinear Network (CNN) templates for implementing linearly-separable one-dimensional (1-D) Cellular Automata (CA). From the gallery of CNN templates presented in this paper, one can calculate any of the 256 1-D CA Rules studied by Wolfram using a CNN Universal Machine chip that is several orders of magnitude faster than conventional programming on a digital computer.

Designing Hardware for FPGAs

The goals of this work are twofold: one is to illustrate the use of Field Programmable Gate Arrays (FPGAs) for emulating circuit elements with memory (memristors, memcapacitors and meminductors). The second goal is to use the FPGA emulation to realize two element chaotic and hyperchaotic circuits. Such circuits utilize fully nonlinear models of memory devices in series-parallel configuration.

Chaotic behaviour in a three element memristor based circuit using fourth order polynomial and PWL nonlinearity

In this chapter we will cover many of the basic concepts behind FPGA design. We start with an overview of our hardware platform, go through a quick introduction to the Quartus toolset and then review combinational along with sequential logic. We will conclude with the all important concept of timing closure. Although we cover a particular hardware platform, the material in this chapter can be adopted to understand other FPGA hardware platforms. This chapter, along with Chap. 1, lay the groundwork for the rest of the book. Nevertheless, please understand that majority of this chapter is meant primarily as a review. However, the conceptual material on abstracting the FPGA development flow via Simulink should not be skipped.