Biju K. Raveendran

Predictive Placement Scheme In Set-Associative Cache For Energy Efficient Embedded Systems

This paper proposes a predictive placement scheme for set-associative cache with better way-prediction hit, energy efficiency and performance. In this work, we consider the data cache subsystem, as it is one of the most power consuming micro-architectural parts of an embedded system. We propose an energy efficient way-prediction scheme with predictive placement to improve prediction hit using minimal prediction bits. We show that, this scheme has an average energy saving 67.75% as compared to conventional caching scheme. Experimental results are obtained using Simplescalar 2.0 cache simulator for SPEC95 benchmarks.

Evaluation of priority based real time scheduling algorithms: choices and tradeoffs

Real time scheduling algorithms like RM and EDF have been analyzed extensively in the literature. Many recent works on scheduling address energy consumption as a performance metric. In this work we analyze priority scheduling algorithms RM, EDF, and LLF along with a few power-aware scheduling algorithms: MLLF, RM_RCS and EDF_RCS. Our analysis addresses the following metrics: response time, response time jitter, latency, time complexity, preemptions, and energy consumption. We extend past work in this direction by characterizing the performance of the scheduling algorithms -- theoretically as well as experimentally. Results of our analysis can be used to control design choices for real time systems.

Energy aware real time scheduling algorithm for mixed task set

Energy consumption is one of the major limiting factors of battery operated real-time systems. Optimizing energy consumption without affecting performance and schedulability is the major topic to be researched. In this paper, an energy aware real time scheduling algorithm is proposed for a system with mixed task set consisting of both periodic and aperiodic tasks. Dynamic energy reduction techniques like Dynamic Voltage and Frequency Scaling (DVFS) is used for energy optimization without affecting the responsiveness of aperiodic tasks. Performance of the proposed algorithm is compared with non-DVS algorithm. Experimental evaluation reveals that the proposed algorithm saves 54.44% of energy in comparison with non-DVS algorithms. It achieves this with no degradation in responsiveness of the aperiodic tasks.

Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors

This paper proposes a novel cache architecture -- Way Halted Prediction -- to reduce energy consumption and effective access time of set associative caches. This is achieved with the help of halt tag array and prediction circuit. Experimental evaluation of various SPEC benchmark programs on CACTI 5.3 and CASIM simulators reveal that the proposed architecture offers 33%, 6% and 3% savings in dynamic energy consumption and 1.80%, 6.13% and -1.95% saving in effective access time over conventional, way predicting and way halting cache architectures respectively.

LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache

This paper proposes a new cache replacement scheme, late least recently used (LLRU). LLRU takes care of shared pages improves its accessibility and offers improved cache performance. LLRU modifies the existing least recently used (LRU) algorithm. This scheme, improves cache performance for applications, which has shared pages. We also propose square matrix and counter based hardware design for LLRU. We show that the proposed scheme will achieve considerable improvement in hit rate. The experimental results are obtained using Simplescalar2.0 cache simulator benchmark. The hardware performance of LLRU counter and square matrix implementation is measured by using Modelsim and Leonardo spectrum.

Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors

Energy optimisation is gaining greater significance in a wide range of systems from mobile devices to datacentres. Specifically, in battery powered real-time embedded systems where tasks are executed under hard timing constraints, energy optimisation poses a big challenge. This paper focuses on dynamic energy optimisation using a well-established technique namely dynamic voltage and frequency scaling (DVFS). This work presents a real-time scheduling algorithm that uses DVFS on mixed task system containing periodic as well as aperiodic tasks on homogeneous multi-core processor. The proposed algorithm guarantees periodic task deadlines and offers minimum aperiodic task response times. Simulation analysis shows that the proposed scheme saves more energy as compared to cycle conserving, static FVS and non-DVFS scheduling algorithms. Further, it does not result in any response time degradation of aperiodic tasks as compared to other algorithms.

DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems

This paper proposes a novel TLB architecture - Deterministic Translation Lookaside Buffer – to reduce TLB misses, energy consumption and effective per access time. DTLB offers tighter upper bound on worst case execution time of real time tasks. This is achieved by backing TLB contents of executing task to PCB on preemption and transferring contents in PCB back to TLB when task resumes its execution. Experimental results carried out using MemSim – a single clock cycle simulator developed in Java with Swing GUI – shows that DTLB gives the least number of TLB misses as compared to conventional TLB model and Reservation based TLB model. DTLB offers on an average 6.74% and 4.91% of dynamic energy savings over conventional model and Reservation based model respectively. Effective access time of DTLB is on an average 2.97% and 2.09% less as compared to conventional and Reservation based model respectively.

eduCloud: a VM communication aware, migration efficient cloud for scientific computing

A computing cloud for research and educational sector should consider different performance factors like reducing VM-VM communication cost, reducing VM migrations, and reducing VM-shared resource communication cost (like a shared file system). This work proposes eduCloud, a cloud for educational institutions with optimised approaches for VM placement, virtual machine (VM) reallocation during cloud fragmentation and cloud consolidation. For reducing communication costs, eduCloud employs a graph-based algorithm which operates on affinity matrix that contains information about magnitude of communication within several VMs. Proposed approach is able to achieve a reduction of 16.44% on average in total communication cost as compared to approaches like vector dot. 5.73% reduction in total communication is achieved over tight fitting approaches like first fit and volume-based. Percentage of in-place unfulfilled demands is reduced by 5.9% as compared to tight fitting algorithms by under provisioning the physical machines maintaining cloud utilisation and resource wastage levels. eduCloud also incorporates reallocation and consolidation routines which decrease communication cost by 5.57%. The distributed version of eduCloud yields very inexpensive Job allocation times of 775.18 ms and 218.43 ms for communicating and non-communicating jobs, respectively.

DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems

Energy consumption plays an important role in designing embedded devices. In recent years, leakage energy gained significant importance in overall energy consumption. This paper addresses leakage energy at operating system level by optimizing scheduler level energy consumption. This is achieved by (i) modifying the first fit allocation algorithm (MFF) to increase shutdown duration of some processors by allocating low frequency tasks to that processors and (ii) maximizing the shutdown duration using dynamic procrastination algorithm (DPS). The procrastination is achieved by postponing the execution of upcoming jobs whenever possible by meeting all timing constraints. This helps in improving shutdown duration along with reducing decision points and static energy consumption. Shutdown decision is based on pre-computed shutdown threshold which is architecture and task set dependent. The experimental evaluation of the proposed algorithm with synthetically generated benchmark program suites shows 88.66%, 14.75% and 1% of saving in total energy consumption over no procrastination (NOPRO) with MFF task allocation, static procrastination (STATICPRO) with MFF task allocation and DPS with FF task allocation respectively.

A survey on replacement strategies in cache memory for embedded systems

Cache is one of the most power-consuming components in computer architecture. Power reduction in cache can be achieved by reducing miss rate miss penalty latency per access and power consumption per access. The power reduction can also be achieved by shutting down unused part of the cache by allowing not so recently used cache banks to sleep reconfiguring the cache for specific application and various combinations of one or more of these. The cache hit depends on the cache size associativity and the cache line size. Replacement strategies in associative mapping schemes play an important role in cache hit rate performance. This survey paper proposes a classification of these strategies with detailed discussion on their advantages and disadvantages.