Bingzhi Su

Design and modeling of RF MEMS tunable capacitors using electro-thermal actuators

A series mounted MEMS tunable capacitor in a CPW line is reported. An electro-thermal actuator has been used for driving the top plate of the parallel plate capacitor. The MEMS structure is bonded on an alumina substrate using flip-chip technology so that the silicon on the backside of the MEMS can be removed to reduce the RF losses. The lumped-element model of the capacitor up to 40 GHz has been developed based on Y-parameters, which are derived from measured S-parameters. The measured Q-factor is 256 at 1 GHz for a 0.102 pF capacitor and C/sub max//C/sub min/ ratio of the capacitor is about 2:1.

The realization and design considerations of a flip-chip integrated MEMS tunable capacitor

Abstract Microelectromechanical systems (MEMS)-based radio frequency (RF) components are being developed for various microwave and millimeter-wave applications. Using standard foundry processes, it is possible to create very complex MEMS devices. However, most RF MEMS need to be fabricated using GaAs, ceramics, high resistivity silicon or other RF-compatible materials. Such fabrication techniques are not commonly used by the mainstream silicon-based MEMS manufacturing infrastructure. As a result, the complexities of these MEMS devices are very limited. What is needed is a way to utilize the existing cost effective foundry processes, but not sacrifice RF performance. Utilizing a flip-chip transfer process, a complex, foundry fabricated, MEMS tunable capacitor has been demonstrated that yields high quality RF performance ( Q ∼100 at 10 GHz, 1050 at 1 GHz). The transfer process is described, and its performance (control, success rate, etc.) is presented. Several major design considerations for implementing the tunable capacitor using flip-chip technology are presented, including warpage, actuator design, and structural rigidity. Using the transfer process and design considerations, there is an opportunity to integrate complex MEMS onto any RF compatible substrate without the silicon semiconductor effects. Thus, it is possible to manufacture complex MEMS cost-effectively for a new generation of RF MEMS with superior functionality.

RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill

RF characterization of flip-chip interconnects in CPW circuits with underfill has been investigated by measuring the scattering-parameters up to 40 GHz for GaAs coplanar waveguide (CPW) through line chips flip-chip mounted on alumina substrate with and without underfill epoxy. Fatigue life of flip-chip assemblies has been computed for different chip sizes and substrates. The results show feasibility of using underfill encapsulant in microwave/mm-wave frequency range.

The effect of underfill epoxy on warpage in flip-chip assemblies

The thermally-induced warpage of both a real flip-chip thermosonically bonded assembly and a simulated tri-layered assembly was investigated. It revealed the warpage of the assemblies was dominated by the forces applied by the underfill epoxy rather than the solder joints. The roles the underfill epoxy and solder joints played in causing warpage did not change even when the assembly had 196 solder joints under a 5.8 mm/spl times/5.8 mm chip. Mechanical properties of epoxy depend on the curing and the glass transition temperatures, and these characteristic temperatures clearly divide the warpage levels into two distinctive regions. When the maximum temperature the assembly was exposed to was less than the glass transition temperature (T/sub g/), the warpage of the assembly was characterized by the curing temperature. When the maximum temperature the assembly was exposed to was higher than T/sub g/, the warpage was characterized by T/sub g/ regardless of how high the temperature was. The distinctive deformation curves with sub-micron repeatability are reported for the first time. Depending upon the different characteristic temperatures of an assembly, e.g., 80/spl deg/C for curing and 130/spl deg/C for T/sub g/, the warpage and the Von Misses stress each could increase by as much as a factor of two. Such an increase could affect device reliability for RF packages and alignment for optoelectronic packages.

Yield prediction for flip-chip solder assemblies based on solder shape modeling

A model has been developed to predict the yield of flip-chip solder assemblies based on calculated solder shapes. It is a physical model considering a limited number of physical factors such as the mean and the standard deviation of the solder volume distribution, the assembly warpage, the die size, and the number of inputs/outputs (I/Os). The main features of the model are: (1) the quick calculation of the solder height of every solder joint out of hundreds or thousands of connections; (2) the definition of failure criteria to determine the assembly yield. The quick calculation is accomplished by the use of a force model to estimate molten solders normal reaction force corresponding to the solders height, volume, circular pad diameter and surface tension coefficient. The failure criteria are height limits determined using surface evolver, which is a public tool for solder shape estimation. Outside the height limits, it is difficult to achieve convergent solutions; therefore, the limits are chosen as failure criteria since they implied large potential manufacturing variations in solder shapes. To illustrate the modeling capability, a case with 1 cm/spl times/1 cm chip, 1024 I/Os is studied. The model shows that a standard deviation of 25% for 4.48 e/sup -7/ cm/sup 3/ mean solder volume produces low yields. The variance of 19% for 4.48 e/sup -7/ cm/sup 3/ is required for a 100% yield.

Solder joint reliability modeling for a 540-I/O plastic ball-grid-array assembly

A three-dimensional finite element model has been developed to study the effects of solder volume and pad size on the reliability of a 540-I/O plastic ball grid array (PBGA) assembly. The model consisted of four parts: solder joint profile model, global model for the PBGA assembly, local model for the single solder joint, and solder joint fatigue life calculation. A submodeling technique was used to transfer the displacements to the local model for a detailed analysis under thermal cycling conditions. By using this model, the effects of solder volume and pad size on the fatigue life of BGA solder joints have been studied. With different volumes or pad sizes, the fatigue life could change from 1800 to 15000 thermal cycles. Since the fatigue life of this PBGA assembly was dominated by local mismatch in most cases, short joints could have longer fatigue lives than those with long joints. In addition, the effect of pad size on fatigue was also increased from second order to a higher order relationship. Such uncommon conclusions resulted from strong coupling effects of solder joint shape, global mismatch, and local mismatch.

Underfill characterization for low-k dielectric / Cu interconnect IC flip-chip package reliability

Due to low dielectric constant inter-metal-dielectric (low-k IMD) materials possessing weaker mechanical properties and higher coefficient of thermal expansion (CTE) compared with IC silicon substrates, the integrity of advanced IC low-k IMD layer/silicon substrate structures, in a packaged form, becomes of great concern. Flip-chip underfill characterization was conducted to investigate the key factors of underfill material properties that can yield good low-k IC package integrity after reliability tests. A simplified stress-coupling-index concept was proposed and used to select five underfills for evaluation, based on their different property characteristics. 27/spl times/27 mm/sup 2/ FCBGA packages with heatspreader were built using 8/spl times/10 mm/sup 2/ low-k test die, and tested by temperature cycling. The test results showed that an FC package with low Tg underfill yielded good performance for low-k package integrity.

The effect of underfill epoxy on mechanical behavior of flip chip assembly

The effect of underfill epoxy on mechanical behavior was investigated by measuring the thermally-induced warpage on both a real flip chip thermosonic bonded assembly and a simulated tri-layered assembly. The assemblys mechanical behavior was dominated by the underfill epoxy rather than solder joints. Such a dominant role was not affected even when the assembly had 196 solder joints under a 5.8 mm/spl times/5.8 mm chip. Epoxy properties are well characterized by the curing and the glass transition temperatures, and these characteristic temperatures clearly divide the warpage levels into two distinctive regions. When the maximum temperature the assembly exposed to was less than the glass transition temperature (Tg), the mechanical behavior was characterized by the curing temperature. When the maximum temperature was higher than the Tg, the behavior was characterized by the Tg. Corresponding to different characteristic temperatures, e.g. 80/spl deg/C for curing and 130/spl deg/C for Tg, the warpage as well as the Von Misses stress each could increase by as much as a factor of two. Such an increase could affect device reliability for RF packages and alignment for optoelectronic packages. With the selected epoxy materials, mechanical behavior of a flip-chip with underfill epoxy is stable and predictable.

Gas flow effects on precision solder self-alignment

Self-aligning soldering technology is being developed for low cost, passive, precision optical alignments. To avoid contamination problems, the solder reflow process must use reacting or inert gas instead of chemical flux materials. Since the accuracy of these optical alignments should reach the range of a few micrometers (/spl mu/m), the gas flow may affect the aligning process. Therefore, the effects of the gas flow on the self-aligning process must be understood. The experiments described show that gas flow effects do exist. The top plate, 8.4 mm/spl times/8.4 mm, can be moved by the gas flow by as much as 4.5 /spl mu/m and 7.8 /spl mu/m at gas flow rates of 2.5 L/min and 5.0 L/min, respectively. The numerical analysis in this study models the gas flow effects for a wide range of chip sizes, solder geometry, and gas flow direction. In the numerical analysis, fluid computation and solder force calculation are conducted to study the gas flow effects on chip displacement that is the distance away from the well aligned position along the gas flow direction. The results show that the gas flow effects are related to many factors including chip size, gas flow rate, solder height, and flow direction. For a one-dimensional (1-D) laser array, these effects are negligible because the chip size is very small. However, for a chip larger than 5 mm/spl times/5 mm, the effects should be controlled for micron-level precision alignment.

Controlled solder self-alignment sequence for an optoelectronic module without mechanical stops

A new flip-chip solder technology has been developed for the precision self-alignment of an optoelectronic module without using mechanical stops. A main feature of the technology is the controlled self-alignment sequence: the laser is aligned to a polymer waveguide in the lateral and vertical directions, then it slowly makes a contact with the waveguide in the axial direction. The elimination of the use of mechanical stops significantly simplifies the process. The axial distance between the laser and the waveguide is very small; it is determined by the edges and a tilt angle of 12/spl deg/. The lateral accuracy is less than 2 /spl mu/m.