Binjie Cheng

Statistical variability and reliability in nanoscale FinFETs

A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and ldquoatomisticrdquo simulations on the same fully calibrated device. The position of the Fermi-level pinning in the polysilicon bandgap that takes place along grain boundaries was evaluated, and polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of polysilicon-gate granularity is highly dependent on Fermi-level pinning position and, consequently, on the structure of the polysilicon-gate material and its deposition and annealing conditions.

Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP

The strategy to generate statistical model parameters is essential for variability-aware design. Based on 3D atomistic simulation results, this article evaluates the accuracy of statistical parameter generation for two industry-standard compact device models.

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs

We present measurements for the standard deviation of the threshold voltage in n- and p-channel MOSFETs from the 45-nm low-power platform of STMicroelectronics. The measurements are compared with 3-D statistical simulations carried out with the Glasgow ldquoatomisticrdquo device simulator, considering random discrete dopants, line edge roughness, and the polysilicon granularity of the gate electrode. It was found that the surface potential pinning at the poly-Si grain boundaries (GBs), which is important for explaining the magnitude of the statistical variability of the n-channel MOSFETs, plays a negligible role in the p-channel case. First-principle simulation of low-angle silicon GBs is performed in order to explain the systematically observed differences in the threshold voltage standard deviation of the measured n- and p-channel MOSFETs.

Statistical Variability in Fully Depleted SOI MOSFETs Due to Random Dopant Fluctuations in the Source and Drain Extensions

Simulations of up to 10 000 fully depleted thin-body silicon-on-insulator MOSFETs show that the standard deviation of the threshold voltage cannot be adequately used as a sole metric of device variability in such transistors. This is due to a sharp departure from normality of the threshold voltage distribution, and an enhanced influence of the source/drain-dopant fluctuations on the on-current and short-channel effects of the fully depleted thin-body silicon-on-insulator transistors. Both aspects have great ramifications for statistical compact models and for low-power SRAM designs.

Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

This paper presents a comprehensive simulation study of the interactions between long-range process and short-range statistical variability in a 14-nm technology node silicon-on-insulator FinFET. First, the individual and combined impact of the relevant variability sources, including random discrete dopants, fin line edge roughness (LER), gate LER, and metal gate granularity are studied for the nominal 20-nm physical gate-length FinFET design. This is followed by a comprehensive study of the interactions of the channel length, fin width and fin height systematic process variations with the combined statistical variability sources. The simulations follow a 3×3×3=27 experiment design that covers the process variability space, and 1000 statistical simulations are carried out at each node of the experiment. Both metal-gate-first and metal-gate-last technologies are considered. It is found that statistical variability is significantly dependent on the process-induced variability. The applicability of the Pelgrom law to the FinFET statistical variability, subject to long-range process variations, is also examined. Mismatch factor is strongly dependent on the process variations.

Impact of Random Dopant Fluctuation on Bulk CMOS 6-T SRAM Scaling

Based on the statistical 3D device simulation of well scaled 25, 18 and 13nm physical gate length bulk MOSFETs, the impact of random dopant fluctuation on 6-T SRAM is studied in detail. The bias control approach is introduced to improve the scalability of bulk CMOS SRAM. Simulation results indicate that at 13nm physical gate length, bulk CMOS SRAM will face fundamental challenges arising from intrinsic parameter fluctuation, and a replacement by ultra thin body SOI CMOS may be necessary at this point

Impact of NBTI/PBTI on SRAM Stability Degradation

We investigate the impact of negative-bias temperature instability (NBTI) on the degradation of the static noise margin (SNM) and write noise margin (WNM) of a SRAM cell. This is based on the quantitative simulation of the statistical impact of NBTI on p-MOSFETs corresponding to a 45-nm low-power technology generation. Due to the increasing importance of positive-bias temperature instability (PBTI) of n-MOSFETs with the introduction of high-/v/metal gate stacks, we also explore the additional impact of PBTI on statistical SNM and WNM degradation behavior. The results indicate that NBTI-only induced SNM and WNM degradations follow different evolutionary patterns compared to the impact of simultaneous NBTI and PBTI degradation, and high distribution moment information is required for the reconstruction of noise margin distributions.

Advanced simulation of statistical variability and reliability in nano CMOS transistors

Increasing CMOS device variability has become one of the most acute problems facing the semiconductor manufacturing and design industries at, and beyond, the 45 nm technology generation. Most problematic of all is the statistical variability introduced by the discreteness of charge and granularity of matter in transistors with features already of molecular dimensions [i]. Two transistors next to each other on the chip with exactly the same geometries and strain distributions may have characteristics from each end of a wide statistical distribution. In conjunction with statistical variability [ii], negative bias temperature instability (NBTI) and/or hot carrier degradation can result in acute statistical reliability problems. It already profoundly affects SRAM design, and in logic circuits causes statistical timing problems and is increasingly leading to hard digital faults. In both cases, statistical variability restricts supply voltage scaling, adding to power dissipation problems [iii]. In this invited paper we describe recent advances in predictive physical simulation of statistical variability using drift diffusion (DD), Monte Carlo (MC) and quantum transport (QT) simulation techniques.

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Conventional bulk CMOS, which is arguably most vulnerable to statistical variability (SV), is the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the SV of key figures of merit on gate geometry, temperature, and body bias in 25-nm gate-length MOSFETs, representative for the 20-nm CMOS technology generation, is systematically investigated using 3-D statistical simulations. The impact of all relevant sources of SV is taken into account. The geometry dependence of the threshold-voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgroms law due to the complex nonuniform channel doping and the interplay of different SV sources. The DIBL variation, for example, follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold voltage, subthreshold slope, ON/OFF currents, and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation, while forward body bias reduces both of them.