Biren Shah

Onboard FPGA-based SAR processing for future spaceborne systems

We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne systems. In particular, we discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

Acquisition performance of various QPSK carrier tracking loops

The frequency and phase acquisition performance of three quadrature phase shift keying (QPSK) carrier tracking loops, the MAP estimation loop, the Costas crossover loop, and the generalized Costas loop, is described. Acquisition time and probability of acquisition as a function of both loop signal-to-noise ratio and frequency offset to loop bandwidth ratio are obtained via computer simulations for type II and III loops. It is shown that the MAP loop, which results in the smallest squaring loss for all signal-to-noise ratios, is sometimes outperformed by the other two loops in terms of acquisition time and acquisition probability. >

Comparison of four FFT-based frequency acquisition techniques for Costas loop BPSK signal demodulation

This paper discussed four open-loop frequency acquisition techniques for suppressed-carrier BPSK signals. The techniques, which do not require accurate symbol timing nor a data preamble sequence, employ fast Fourier transforms (FFTs) on the Costas loop phase detector output to detect the Doppler frequency offset. Performance of the full-, half-, and staggered-symbol integration techniques as well as the low-pass filter technique are compared in terms of the error signal output SNRs. Then, the probability of detecting the frequency offset is computed for the special case when the frequency of the tone to be detected coincides with one of the FFT-bin center frequencies. It is shown that the performance of the integration techniques depends strongly on the symbol timing offset. On the other hand, the detection probability for the one-pole arm filter technique depends directly on the filter bandwidth. The staggered integration technique is shown to have comparable performance to the low-pass filter technique for low-to-medium symbol SNRs but the latter is superior at high symbol SNRs. >

Comparison of two maximal ratio combining techniques in antenna arraying

When signals from a user (fixed or mobile) are received at multiple antennas, the signals can be arrayed to increase the signal-to-noise ratio (SNR) of the received signal. This article describes two maximal ratio combining techniques referred to as full spectrum combining (FSC) and complex symbol combining (CSC), and then compares them in terms of the achievable arraying gain. Although the performance of these techniques is derived for the case of binary phase shift keying (BPSK) signalling in an additive white Gaussian noise channel, the analytical techniques here are applicable to other modulations and channels. The paper also addresses the use of symbol SNR degradation and symbol SNR loss as system performance measures. It is shown that degradation and loss are equal at weak signal levels but degradation is a lower bound for loss when the signal is strong. The telemetry arraying techniques described are applicable to any phase modulated signal. We assess the deep space communication channel performance scenario where the weakest signals ever are detected.

Application of multirate digital filter banks to wideband all-digital phase locked loops design

A new class of architecture for all-digital phase locked loops (DPLLS) is presented. This architecture, referred to as parallel DPLL (PDPLL), is based on employing multirate digital filter banks (DFBs) to track signals with a lower processing rate than the Nyquist rate, without reducing the input (Nyquist) bandwidth. The PDPLL basically trades complexity versus hardware processing speed by introducing parallel processing in the receiver. A reduced complexity DFB that is ideal for implementation of the PDPLL is introduced. It is demonstrated that the PDPLL performance is identical to that of a DPLL for both steady state and transient behavior. Various Doppler characteristics are used to compare the performance of the DPLL with the PDPLL.<<ETX>>

A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors

Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly-used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.

Design of wideband all-digital phase locked loops using multirate digital filter banks

All-digital phase locked loops (DPLLs) have many advantages over analog loops. However, due to digital device limitations and costs, superwide PLLs with front-end bandwidths as high as one gigahertz are commonly implemented using analog parts. This article presents a new architecture that allows an all-digital implementation of superwide PLLs. The problem of operating digital components at high speed is avoided here (without reducing the front-end bandwidths) by inserting a multirate digital filter bank in front of the DPLL. The new design is shown to have steady-state and transient performance that is identical to a conventional DPLL.

A functional description of the buffered telemetry demodulator for the Galileo mission to Jupiter

The paper functionally describes a novel buffered telemetry demodulator (BTD) for the Galileo spacecrafts upcoming encounter with Jupiter. Due to an inoperative high gain antenna the Galileo signal is characterized by low data rates and an extremely weak space-to-ground communication link. The extremely weak downlink is expected to result in an unusually long acquisition time and frequent cycle slips. In this case, the BTD is most useful as it operates on recorded (or buffered) digital samples to extract symbols from the received signal. The key features of the BTD are (1) its ability to reprocess the signal to reduce acquisition time and enable resynchronization, (2) its ability to use future information about the signal and perform smoothing in the past to recover symbols lost during acquisition and resynchronization, (3) its minimized recording bandwidth as each harmonic of a square-wave subcarrier is recorded individually, and (4) its parallel architecture that enables a multi-processor implementation. The paper discusses baseband recording and demodulation schemes, as well as, the computational speed required to implement the BTD in software. Several general purpose computers that can be used for implementation are identified.<<ETX>>

Ka-band tone generator for the ISARA Cubesat

This paper describes the design and fabrication of a 26GHz tone generator for the ISARA Cubesat. The tone generator uses a phase locked loop (PLL) frequency multiplier to get to 26GHz from an on board temperature compensated crystal oscillator (TCXO). The output of the PLL feeds a solid state power amplifier (SSPA) that puts out approximately 27dBm of RF power. The SSPA output then feeds a monolithic microwave integrated circuit (MMIC) switch which toggles between a high gain and low gain antenna as part of the ISARA experiment. The microwave electronics is packaged in an aluminum chassis and utilizes hybrid assembly technology. There are bare die with ribbon and wire interconnects in addition to printed circuit boards (PCB) which use surface mount technology (SMT) for assembly. Custom distributed circuits were designed for implementing the 26GHz filters, couplers and power detectors. A key aspect of this modules performance is its overall thermal stability which is highly dependent upon its assembly technology. The order of operations of each assembly phase, attachment materials, contamination control and reliability of interconnects all determine how well the hardware performs in flight.

Adaptation of the Electra radio to support multiple receive channels

Proposed future Mars missions plan communication between multiple assets (rovers). This paper presents the results of a study carried out to assess the potential adaptation of a proximity link relay radio (i.e., the Electra radio) to a multi-channel transceiver. The basic concept is a Frequency Division multiplexing (FDM) communications scheme wherein different receiver architectures are examined. Options considered include: (1) multiple IF slices, A/D and FPGAs each programmed with an Electra baseband modem; (2) common IF but multiple A/Ds and FPGAs and (3) common IF, single A/D and single or multiple FPGAs programmed to accommodate the FDM signals. These options represent the usual tradeoff between analog and digital complexity. Given the space application, a common IF is preferable; however, multiple users present dynamic range challenges (e.g., near-far constraints) that would favor multiple IF slices (Option 1). Vice versa, with a common IF and multiple A/Ds (Option 2), individual AGC control of the A/Ds would be an important consideration. Option 3 would require a common AGC control strategy and would entail multiple digital down conversion paths within the FPGA. In this paper, both FDM parameters as well as the different Electra design options will be examined. In particular, signal channel spacing as a function of user data rates and transmit powers will be evaluated. In addition, tradeoffs between the different Electra design options will be presented with the ultimate goal of defining an augmented Electra radio architecture for potential future missions.1,2