Bishwajeet Pandey

SSTL based green image ALU design on different FPGA

In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40 nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes of SSTL and observe that when image ALU operates at 1 THz device operating frequency with SSTL18_I_DCI I/O Standard using virtex-6 FPGA, there is 45.55% decrease in IO power and 20.50% in Clock power as compared to SSTL18_II IO Standard. Similarly when we operate Image ALU at 1 THz using Spartan-6, there is 33.31% reduction in IO power of SSTL18_I with respect to SSTL18_II Standard. There are 16 different arithmetic and logic operations in Image ALU. The Clock power, Logic power and Signal power of Image ALU remains same using Spartan-6 I/O Standard.

Thermal aware energy efficient bengali unicode reader in Text analysis

In Text analysis, the current focus of researcher is on performance. There is a wide research gap to design energy efficient hardware which is in use in text analysis. When room temperature is 25 degree Celsius, there is 60.01%, 39.98%, 20% reduction in Clock Power when we scale down device operating frequency from 250GHz to 200GHz, 150GHz and 100GHz respectively. When ambient temperature is 50 degree Celsius, there is 55.56%, 33.33%, 16.67% reduction in Logic Power when we scale down device operating frequency from 250GHz to 200GHz, 150GHz and 100GHz respectively. When ambient temperature is 75 degree Celsius, there is 59.91%, 39.67%, 19.83% reduction in Signal Power when we scale down device operating frequency from 250GHz to 200GHz, 150GHz and 100GHz respectively. When ambient temperature is 100 degree Celsius, there is 60%, 40%, 20% reduction in IOs Power when we scale down device operating frequency from 250GHz to 200GHz, 150GHz and 100GHz respectively. With Thermal Scaling, there is no change in Clock Power, Logic Power, Signal Power and IOs Power. There is 26.56%, 64.73%, 79.46% significant reduction of leakage power when we scale down ambient temperature from100 C to 75 C, 50 C and 25 C.

I/O standard based thermal/energy efficient green communication for Wi-Fi protected access on FPGA

In this paper, we analyzed how does life and reliability of an integrated circuit is affected when it is operated in different regions under different temperatures. We have taken Fibonacci generator as our target circuit and LVCMOS as I/O standards. WPA and WPA2 (Wi-Fi Protected Access) key can be generated with Fibonacci generator. Here, thermal efficient green Fibonacci Generator is used to generate key for Wi-Fi Protected Access in order to make green communication possible under different room temperature. By analysis it is observed that at standard normal temperature (21°C), LVCMOS12 have 24%, 17.3% and 95.53% less junction temperature than LVCMOS25 at operating frequencies of 1 GHz, 10 GHz, and 100 GHz respectively, while at 1 THz, the junction temperature becomes 125°C, which causes unreliability for circuit and device may not operate at that frequency. For worlds highest temperature (56.7°C), we achieve 0.97% and 8.29% reduction in junction temperature at 1 GHz and 10 GHz operating frequencies respectively. This design is implemented in verilog on virtex-6 FGPA. Usually for functioning of a device, the junction temperature is below 125°C.

Output load capacitance based low power implementation of UART on FPGA

Core dynamic power is independent of output load capacitance. IO power and static power is dependent on output load capacitance. In this work, we achieved 99.72% reduction in IOs power consumption of Universal Asynchronous Receiver Transmitter (UART) if we scale down output load from 10,000pf to 5pF in IOB setting of FPGA. Universal Asynchronous Receiver and Transmitter are a transceiver circuits that transmit/receive data between parallel and serial forms and vice versa. Design state of our design is high because no black box found. Bit width is high because 57.6% of primitives in RTL net list represent 1-bit logic. Here, IO power consumption is 17,226mW on 10,000pF output load which significantly reduce to 47mW on 5pF output load. Along with reduction in IOs power, we also observed 24.5% reduction in static power consumption from 1322mW on 10,000pF output load to 1004mW on 5pF output load. In our implementation on FPGA, we take Virtex-6 family, XC6VLX75T device, FF484 package, -1 speed grade, XST synthesis tool, ISim simulator, and Verilog as preferred HDL language.

Capacitance scaling based energy efficient FIR filter for digital signal processing

In this work, we are implementing FIR Gaussian low pass filter using DSP slice available in 28nm Kintex-7 FPGA. In order to make energy efficient filter, we are using capacitance scaling. During capacitance scaling, we observe that there is no change in clock power, logic power, signal power and DSP power. But, there is significant reduction in IOs power, leakage power and total power of FIR filter on 28nm Kintex-7 FPGA. There is approx 44.74% reduction in IOs power when FIR filter operating frequency is 5GHz, 50GHz, 500GHz and 1THz and capacitance is scaled down from 25pF to 5pF. There is approx 87.65% reduction in leakage power when FIR filter operating frequency is from 500GHz to 5GHz. There is approx 99.51% reduction in leakage power when FIR filter operating frequency is from 1THz to 5GHz.

Design of power optimized memory circuit using High Speed Transreceiver Logic IO Standard on 28nm Field Programmable Gate Array

In this work, we designed a power efficient memory circuit using family of various HSTL IO Standards on 28nm Field Programmable Gate Array (FPGA). Nine different HSTL IO Standards are compared with each other to search the most power efficient one. We validated our circuit with different HSTL IO Standards and on Different frequency range to obtain a most power efficient circuit. In our experiment, there is 87.44% power reduction when HSTL_I is replaced with HSTL_I_DCI_18 on 1 GHz frequency and 76.32% power reduction where we use HSTL_I_12 at place of HSTL_I_DCI_12. According to this experiment, HSTL_I is proved a best energy efficient IO Standard when compared with any other family of HSTL. To design this energy efficient memory circuit we are using Verilog as HDL, Xilinx ISE14.6 simulator with kintex-7 FPGA.

Digitally controlled impedance based green design on ultra scale FPGA

In this paper LVDCI, LVDCI_DV2 and HSLVDCI I/O standards are used to make green Fibonacci generator. We have taken 3 classes for each LVDCI, LVDCI_DV2 and HSLVDCI. LVDCI_15 has 53-54% less I/O power requirement than LVDCI_25. We achieve 65-66% power reduction with LVDCI_DV2_15 in compare to LVDCI_DV2_25. In order to achieve energy efficiency along with high performance, when we use high speed variant of LVDCI i.e. HSLVDCI_15 has 55% less I/O Power reduction than HSLVDCI_25 along with significant reduction in time to implement this design. In this work, we are using device operating frequencies in range of 1 GHz-1 THz. This is implemented in verilog on 40 nm ultra scale FPGA. For verification and validation of functionality of Fibonacci generator, we write verilog test fixture and simulate in Isim.

Capacitance and frequency scaling based energy efficient image inverter design on FPGA

In this work, Capacitance scaling and Frequency scaling is done in order to make energy efficient Image Inverter design. Frequency scaling results variations in power consumption and the Junction temperature of Image Inverter. There is 93.33% change in Logic power, 98.06% change in Signals power, 99.00%change in IOs power, 92.02% change in Leakage power and 77.6% change in Junction temperature. Clocks power, Logic power and Signal powers are independent of the capacitance scaling while the frequency is constant. At the same time IOs power, Leakage power as well as the Junction temperature varies. Along with fixed 1GHz frequency it is found that there is 71.92% increment on IOs power while capacitance is incremented by 90%. At the same time there is a 2.4% increment found in Leakage power while Junction temperature faces an change of 7.14%.

Reliable ALU design with optimized voltage and implementation on 28nm FPGA

In this work 40nm Virtex-6 and 28nm Artix7 is target Device. Xilinx 14.2 ISE is a Design tool, ALU is target Design. In this work, we apply voltage optimization to reduce dynamic power in both 28nm and 40nm technologies. With the help of voltage optimization, there is 93.74%, 93.64%, 93.52%, 93.51% and 93.54% reduction in power on 28nm for range of 1V-0.5V with step size of 0.1V on 100 MHz in comparison to power consumption on 40nm. There is 90.65%, 90.04%, 89.48%, 89.13% 88.99 and 88.88% reduction in power on for range of 1V-0.5V with step size of 0.1V on 1 GHz in comparison to 40nm technology FPGA. There is 69.39 %, 66.78%, 64.81%, 63.38%, 62.47% and 61.92% reduction in power on 28nm technology for range of 1V-0.5V with step size of 0.1V on 10 GHz. 32.86 %, 30.77%, 29.24%, 28.10%, 27.25% and 26.57% power reduction is possible on 28nm technology for range of 1V-0.5V with step size of 0.1V on 100 GHz. If device operating frequency is 1 THz, then 19.28%, 19.05%, 18.79%, 18.48%, 18.14% and 17.74% reduction in power on 28nm technology is possible for range of 1V-0.5V with step size of 0.1V on in comparison to power consumption of 40nm technology. 28nm Technology based FPGA is more power effective FPGA in comparison to 40nm technology based FPGA. On 100 MHz, power reduction is maximum i.e. 93.74%. On 1 THz, it is minimum i.e. 19.28%. Voltage Scaling is able to reduce total power consumption in range of 93.74%-19.28%.

64 bit green ALU design using clock gating technique on ultra scale FPGA

In this paper 64-bit energy efficient Arithmetic Logic Unit (ALU) is designed in verilog with the help of clock gating technique. We can reduce dynamic power and dynamic current of 64-bit ALU by using clock gating technique. This design is implemented on XC6VLX75T device, -3 speed grade and Virtex-6 FPGA. When clock logic is applied to target device, we are achieving 67.74% and 65.84% less reduction in clock power and 93.82% and 93.71% less reduction in Leakage power, when the device is operating on frequencies 1GHz and 10GHz respectively. On 1GHz, there is 66.93% less reduction in overall dynamic power of 64-bit ALU, when clock gate is added to the device. Dynamic current is reduced to 39.53% at operating frequency of 1THz, when clock gating is used.