Biswajit Bhowmik

An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers

Previous works on detecting and locating manufacturing faults-shorts, stuck-at, and open on an interswitch link of a channel in a network-on-chip (NoC) have been based on the assumption that these faults do not coexist. The works failed to diagnose all these faults when this assumption is relaxed. A deficiency for non-diagnosability of these faults is then represented. A packet address driven test strategy that detects and locates a faulty inters witch link in a NoC channel is proposed. The strategy addresses the intra-channel shorts, stuck at, and open faults coexist on inters witch links and is governed by parallel activation of diagonal routers. The strategy is scalable with mesh NoCs. Simulation results achieve 100% and more than 97% fault coverages when faults are diagnosed explicitly and implicitly respectively.

Detection of faulty interswitch links in 2-D mesh network-on-chips

The network-on-chip has become an emerging research area in the fields of system on chips, embedded systems, integrated circuits design, etc. with the rapid advancement of technologies. The introduction of multi-core chips has in addition made researches in the area ever significant and is growing to facilitate high demand of bandwidth via core utilization and need of scalable interconnection fabrics. Numerous technical papers have addressed the performance evaluation but a limited attention has been paid on detection of faulty interswitch links in post manufactured network-on-chip setups. Existing works are traditional circuit based but not with respect to current aspects. Main drawbacks of these approaches are high detection time, large test data, and low scalability. In this paper we propose a novel high level detection model for interswitch links in network-on-chips. The detection process is exercised with a set of test patterns to identify faulty links. The model proposes both local and global test generation schemes. A 2-D mesh network-on-chip architecture is considered for experiment. The experimental results show that the proposed detection model outperforms with a finite test patterns set which suffices to test all interswitch links of the underlying network-on-chip.

An odd-even model for diagnosis of shorts on NoC interconnects

Interconnect shorts in a network-on-chip (NoC) have caused data overloading and misrouting that make an extra burden on performance metrics. Therefore, diagnosis of shorts on NoC interconnects has taken special interest. Existing works on diagnosis of shorts on NoC interconnects have two major issues-high test time and less scalability. This paper presents a distributed packet address driven test strategy that addresses shorts on NoC interconnects and tackles these issues. High test time is reduced significantly by lowering the test rounds. The scalability is established by applying proposed test strategy on different NoCs. Simulations achieve 100% test and fault coverages, and demonstrate impact of interconnect shorts for a subset of performance metrics in actual traffic in the network.

Impact of NoC interconnect shorts on performance metrics

Duplication, misrouting, and dropping of packets due to short faults on network-on-chip (NoC) interconnects have become a burden and significant impact on performance metrics. This paper proposes an adaptive approach that detects and locates intra-channel short faults on NoC interconnects, and accounts impact of the faults on performance metrics. The model is scalable with all NoCs. Simulations show the effectiveness of proposed approach and measure different performance metrics with faulty channels on various NoCs.

A matrix model for redefining and testing NoC interconnect shorts

Network-on-chip (NoC) has currently considered as a holistic solution over traditional and global bus-based system-on-chip (SoC) interconnections. However, NoC interconnects experience a subset of manufacturing faults- shorts, opens, and stuck-ats. A limitation of prior works on testing shorts on interconnects of a NoC is that interconnects are tested without coexistent open faults. The works then fail to detect all shorts if a relaxation is made on this assumption. A fast matrix based test strategy that tests and diagnoses shorts with and without coexistent opens on NoC interconnects is proposed. Proposed strategy is scalable irrespective of NoCs and evaluated in terms of test time, test criteria, and performance metrics. Both 100% and near 100% fault coverages are achieved on explicit and implicit testing of shorts respectively. However, 100% test coverage is achieved in either of the cases.

A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects

With the rapid advancements of deep submicron and nano technologies the dimension of a chip is ever shrinking. With continuous shrinking of chip dimensions, immense interconnects are associated on a die to satisfy high bandwidth requirements and make a network-on-chip (NoC) architecture prone to large number of interconnect faults. Therefore the reliability becomes a crucial issue for the communicating parties in a NoC communication fabric. This paper presents a packet address driven test strategy that diagnoses NoC interconnects experiencing stuck-at (stuck-at-0 and stuck-at-1) faults. The proposed strategy is scalable to all sizes and types of mesh NoCs and can be extended to other NoCs. The simulation is done on a number of mesh NoCs to establish the scalability. The simulation results show the performance measured in terms of test and fault coverages that can reach to 100% at the expense of few CPU clocks.

Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects

A scalable, packet address driven strategy that tests an open fault on network-on-chip (NoC) interconnects and maximal connectivity between neighbor routers in presence of a short fault is proposed. The open faults and maximal connectivity are tested for data, control, and handshake interconnects by the proposed method using finite test sequence. Experiments ensure the state of faultiness/non-faultiness of an interconnect with/without an open fault and possibility of connectivity over faulty interconnects for a channel. Evaluation is done in terms of test time, testing criteria, and performance metrics. Results achieve 100% test and fault coverages when interconnects possess open faults only but nearly 100% when shorts are injected on faulty interconnects to make connectivity.

An on-line test solution for addressing interconnect shorts in on-chip networks

This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traffics.

A topology-agnostic test model for link shorts in on-chip networks

With the ever-shrinking global geometries on a die and the concomitant rise in the complexity of interconnections in an on-chip network (NoC), the links used therein often suffer from various manufacturing defects such as shorts. These defects not only cause logical or functional errors but also give rise to various other system level failures such as duplication, misrouting, or dropping of a packet, thereby impacting the performance of the network significantly. This paper proposes an on-line test method that detects the presence of pairwise-shorts, if any, and identifies the faulty links. Several performance metrics are evaluated to demonstrate the impact of these faults, and simulation results demonstrate 100% coverage. The proposed method scales well to large-size NoCs irrespective of the topology and link-width.

On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems

This paper presents a distributed on-line test mechanism that detects stuck-at faults (SAFs) in the channels as well as identifies the faulty channel-wires in an on-chip network (NoC). The proposed test mechanism improves yield and reliability of NoCs at the cost of few test clocks and small performance degradation. Additionally, the mechanism is scalable to large-scale NoCs. We study the impact of channel stuck-at faults on various performance metrics and simulation results establish 100% coverage metrics and the effectiveness of the proposed test mechanism.