Bivragh Majeed

Sloped Through Wafer Vias for 3D Wafer Level Packaging

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profde which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250degC) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mOmega depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.

Photoresist coating and patterning for through-silicon via technology

Three-dimensional (3D) integration requires through-wafer interconnects, i.e. an integration of electrical connections from one side of the wafer to the other side. In some cases, it involves the lithographic patterning of through-Si via (TSV). For this step, a conformal coating of a resist layer is necessary. In this paper, we present two potential photoresist coating methods for coating a wafer with TSV: spray coating and electrodeposition (ED) of the photoresist. Lithographic patterning inside the TSV is also investigated. Some parameters that influence the pattern definition, such as large gap exposure, resist thickness and via size, are identified and evaluated.

Parylene N as a dielectric material for through silicon vias

This paper reports on the feasibility of parylene N as a dielectric material for through silicon vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First, the thickness uniformity of as-deposited parylene across the wafer and inside the via is investigated. The results show that for 200 mm wafers, within-wafer and wafer-to-wafer thickness is sufficiently uniform. The 1-sigma thickness variation of less than 4 percent for both cases is measured. 1 sigma thickness variation of less than 5 percent is observed from batch to batch. Second, the effect of substrate, temporary glue layer and carrier wafer for thinned device wafers on the dry etching of parylene is analyzed. The experiments show that the etching was sufficiently uniform across the wafer; and the uniformity across the surface is recorded to be greater than 95 percent. There is no considerable effect of substrate or bonding layer thickness, however carrier wafer influence the etching rate.

Silicon Based System for Single-Nucleotide-Polymorphism Detection: Chip Fabrication and Thermal Characterization of Polymerase Chain Reaction Microchamber

A single nucleotide polymorphism (SNP) is a difference in the DNA sequence of one nucleotide only. We recently proposed a lab-on-a-chip (LoC) system which has the potentiality of fast, sensitive and highly specific SNP detection. Most of the chip components are silicon based and fabricated within a single process. In this paper, the newly developed fabrication method for the silicon chip is presented. The robust and reliable process allows etching structures on the same chip with very different aspect ratios. The characterization of a crucial component to the LoC SNP detector, the microreactor where DNA amplification is performed, is also detailed. Thanks to innovative design and fabrication methodologies, the microreactor has an excellent thermal isolation from the surrounding silicon substrate. This allows for highly localized temperature control. Furthermore, the microreactor is demonstrated to have rapid heating and cooling rates, allowing for rapid amplification of the target DNA fragments. Successful DNA amplification in the microreactor is demonstrated.

A wireless inertial measurement system (WIMS) for an interactive dance environment

This paper will present the work carried out in designing a Wireless Inertial Measurement System (WIMS) designed for a wearable system operating in an interactive dance environment. The concept underpinning this system is the generation of inertial information from multiple nodes distributed over a dancers body, which will enable the dancer to communicate with their environment and interact with their surroundings through movement. The IMU nodes will be arranged in a network configuration whose control will be based upon existing technology developed at Tyndall.

Development and characterisation of ultra thin autonomous modules for ambient system applications using 3D packaging techniques

The work presented in this paper represents two strands of the work of the ambient system team at NMRC to produce ultraminiature sensor modules (K. Delaney et al, Proc. 40th IMAPS Nordic Conf., pp. 13-21, 2003). These modules with an ultimate target size of <1 mm/sup 3/ are needed for the implementation of future ad-hoc networks for ambient systems. Ambient systems stem from convergence of three key technologies: ubiquitous computing, ubiquitous communication and intelligent user friendly interfaces. On convergence, humans will be surrounded by intelligent interfaces, supported by computing and networking technology which is everywhere, embedded in everyday objects such as furniture, clothes, vehicles, and smart materials. The work done for the realisation of the 1 mm/sup 3/ autonomous sensor module is following a technology roadmap developed by NMRC. The work is carried out in different phases: in the first phase a 25 mm cube fabricated as 3D stackable modular PCB is being reported (J. Barton et al, UbiComp 2002, and ICEWES 2002). The current module is a 1 cm cube, combining a microcontroller, PLD, accelerometer, light dependant resistors and coloured LEDs with the aim of creating modular wireless computational unit (J. Barton et al, Proc. 53rd Electron. Comp. and Tech. Conf., 2003). This paper details the assembly, characterisation and reliability issues of this module while work done to realise a very thin multi layer flexible substrate for a 5 mm cube is presented.

Ion-pair reversed-phase chromatography of short double-stranded deoxyribonucleic acid in silicon micro-pillar array columns: Retention model and applications

Separation of double-stranded (ds) DNAs is important in numerous biochemical analyses relevant for clinical applications. A widely used separation technique is high performance liquid chromatography (HPLC), in the variant of ion-pair reversed-phase (IP-RP) chromatography. HPLC can be miniaturized by means of silicon micro-pillar array columns leading to on-chip fast and high resolution dsDNA separation with limited sample quantity. However, theoretical studies of retentive behavior of dsDNA in miniaturized chromatographic columns are hardly available, despite their enormous practical relevance. This paper established a new retention model to describe the size dependent separation of dsDNAs for any characteristic of the linear mobile phase gradient, in analogy to the model used to describe the retention of polymer chains with repeating units in RP HPLC. The model agrees with a large amount of dsDNA retention data, measured using DNA molecules in the size range of 10-400 base pairs in columns with different lengths (2 and 40cm) and different micro-pillar sizes (2 and 2.5μm in diameter), in various mobile phase gradients. The model is particularly useful in practice, since it requires no numerical solutions and the column-specific fitting parameters (4 or 5) can be determined in a limited number of separation runs. As examples of its applications, the model has been used for the optimization of dsDNA step-gradient separations (5 dsDNAs separated within 8min) and for the determination of the size of dsDNA fragment (with uncertainty of about 2%). These applications are especially relevant for on-chip DNA analysis devices.

Microstructural, mechanical, fractural and electrical characterization of thinned and singulated silicon test die

This paper investigates the effects of thinning on different properties of silicon test die. Silicon test wafers of different thicknesses (525, 250, 100 and 50 µm) were thinned using a mechanical grinding process. The wafers were diced by using a specialized dicing saw and by a laser to study the effect of singulation. The laser dicing adversely affected the mechanical properties, while the fracture strength and flexibility increased with a reducing die thickness for mechanical grind test die. Fractured dies were macro and microscopically examined indicating different modes of failure depending on the fracture load. The electrical parameters of the test die were investigated and showed no adverse affect on the properties due to the thinning process.

Micron-sized pillars for ion-pair reversed-phase DNA separations

In the present paper, the feasibility to construct micron-sized silicon pillar channels to be used in HPLC is studied. For this, a channel with flow-through pores of 1 μm and with critical sidewall dimensions below 1 μm was constructed using advanced deep-UV lithographic equipment. Integrating a 3-nL injection system on the chip directly in front of the separation channel and using elongated distribution structures, a very controlled and high aspect ratio sample definition across the relatively wide separation channel was accomplished. The system was evaluated in isocratic ion-pair RP mode, allowing the separation of a mixture of two components with, respectively, 300 and 400 base pairs in 5 s only.

Design and fabrication of a biomedical Lab-on-Chip system for SNP detection in DNA

A Lab-on-Chip system is proposed, capable of SNP (Single Nucleotide Polymorphism) detection in DNA. One of the core components is an advanced filter consisting of an ordered array of Si micro-pillars enabling fast and effective separation of 5 DNA segments with different length using chromatographic techniques. Also a dedicated micro-pump is fabricated based on conductive polymer actuation, generating the required high pressure to sustain the fluid flow through the total system. For the detector, a known detector principle is applied, but pronounced miniaturization is carried out in order to make a small and portable system.