Bong-gi Kim

Cost-effective process integration for a high performance 0.5 /spl mu/m CMOS logic device

A high performance and cost-effective process for a 0.5 /spl mu/m CMOS logic device optimized for 3.3 V has been developed. To fill contacts and via holes, an in-situ Al reflow technique was employed instead of the high cost W-plug process. It was found that the in-situ Al reflow technique was very effective in improving the electrical properties and reliabilities of the multilevel interconnects. Quasi-global inter-metal-dielectric (IMD) planarization has been achieved by the COmbining PHOtoresist etchback and SOG etchback (COPHOS) process.

Series resistance at metal contact for thin film SOI MOSFET

Thin-film silicon-on-insulator (TFSOI) MOSFET has emerged as a strong candidate for high performance, high density and latch-up free CMOS devices with less fabrication steps. Thin silicon film should be used to achieve good behavior in SOI MOSFET. However, most of the papers on TFSOI have reported high parasitic source/drain series resistance and contact resistance, which tends to obscure the performance advantages of SOI. In this paper, we examined effects of top silicon film thickness (Tsi) on contact series resistance and contact hole etching method.