Bongkyu Lee

Data Distribution of Road-Side Information Station in Vehicular Ad Hoc Networks (VANETs)

Vehicular Ad Hoc Networks (VANETs) have received large attention in recent times. There are many applications bringing out the new research challenges in the VANET environment such as vehicle to vehicle communication, road-side vehicle networking etc. Road-side data access in the two intersecting roads of downtown area in VANET is the main consideration of this paper. Caching is a common technique for saving network traffic and enhance response time, especially in wireless environments where bandwidth is often a scare resource. In this paper, a novel Road-Side Information Station (RIS) data distribution model with cache scheme in VANET for the data access in the two intersecting roads of downtown area is proposed. The performance of the proposed scheme is tested through simulations. The simulation results reveal that the proposed scheme can significantly improve the response time, and the network performance.

Secure Steganographic Model for Audio e-Book Streaming Service

We present steganographic service model and algorism that fit feature of streaming audio book service in order to hide information of copyright and certificate of it. Secret information is encrypted with random numger by secret key that client and server share, so that increase confidentiality. We made secret data distributed randomly and evenly, and improved throughput by simplifying additional computations considering streaming environment.

IPSec Key Recovery for IKEv2

IPSec is the security protocol that do encryption and authentication service to IP messages on network layer of the internet. This paper presents the key recovery mechanism that is applied to IKEv2 of IPSec for mobile communication environments. It results to have compatibility with IPSec and IKEv2, reduce network overhead, and perform key recovery without depending on key escrew agencies or authorized party.

Design and Implementation of Hardware for various vision applications

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

Performance evaluation of parallel systems employing roll-forward checkpoint schemes

High performance and reliability are the main goals of parallel and distributed computing systems. To increase the performance and reliability of the systems, various checkpoint schemes have been proposed in the literature for decades. However, the lack of general analytical models has been an obstacle to compare the performance of systems employing different checkpoint schemes. This paper develops an analytical model to evaluate the relative response time of systems employing checkpoint schemes. The model has been applied to evaluate the relative response time of systems employing RFC (Roll-Forward Checkpoint), DMR-F (Double Modular Redundancy for Forward recovery), and DST (Duplex with Self-Test) schemes. The result shows the feasibility of the model developed in the paper.