Boris Murmann

A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

The multi-bit first stage of a 12 b 75 MS/s pipelined ADC uses an open-loop gain stage to achieve more than 60% residue amplifier power savings over a conventional implementation. Statistical background calibration removes linear and nonlinear residue errors in the digital domain. The prototype IC achieves 68.2 dB SNR, -76 dB THD, occupies 7.9 mm/sup 2/ in 0.35 /spl mu/m CMOS and consumes 290 mW at 3 V.

Matrix-insensitive protein assays push the limits of biosensors in medicine

Advances in biosensor technologies for in vitro diagnostics have the potential to transform the practice of medicine. Despite considerable work in the biosensor field, there is still no general sensing platform that can be ubiquitously applied to detect the constellation of biomolecules in diverse clinical samples (for example, serum, urine, cell lysates or saliva) with high sensitivity and large linear dynamic range. A major limitation confounding other technologies is signal distortion that occurs in various matrices due to heterogeneity in ionic strength, pH, temperature and autofluorescence. Here we present a magnetic nanosensor technology that is matrix insensitive yet still capable of rapid, multiplex protein detection with resolution down to attomolar concentrations and extensive linear dynamic range. The matrix insensitivity of our platform to various media demonstrates that our magnetic nanosensor technology can be directly applied to a variety of settings such as molecular biology, clinical diagnostics and biodefense.

A/D converter trends: Power dissipation, scaling and digitally assisted architectures

This paper summarizes recent trends in the area of low-power A/D conversion. Survey data collected over the past eleven years indicates that the power efficiency of ADCs has improved on average by a factor of two every two years. A closer inspection on the impact of technology scaling is presented to explain the observed trend in the context of shrinking supply voltages and increasing device speed. Finally, a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.

Highly stretchable polymer semiconductor films through the nanoconfinement effect

Trapping polymers to improve flexibility Polymer molecules at a free surface or trapped in thin layers or tubes will show different properties from those of the bulk. Confinement can prevent crystallization and oddly can sometimes give the chains more scope for motion. Xu et al. found that a conducting polymer confined inside an elastomer—a highly stretchable, rubber-like polymer—retained its conductive properties even when subjected to large deformations (see the Perspective by Napolitano). Science, this issue p. 59; see also p. 24 A high-performance conjugated polymer is combined with an elastomer to produce a fully stretchable transistor. Soft and conformable wearable electronics require stretchable semiconductors, but existing ones typically sacrifice charge transport mobility to achieve stretchability. We explore a concept based on the nanoconfinement of polymers to substantially improve the stretchability of polymer semiconductors, without affecting charge transport mobility. The increased polymer chain dynamics under nanoconfinement significantly reduces the modulus of the conjugated polymer and largely delays the onset of crack formation under strain. As a result, our fabricated semiconducting film can be stretched up to 100% strain without affecting mobility, retaining values comparable to that of amorphous silicon. The fully stretchable transistors exhibit high biaxial stretchability with minimal change in on current even when poked with a sharp object. We demonstrate a skinlike finger-wearable driver for a light-emitting diode.

HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13

A power and area efficient sensor interface consumes 6.4 mW from 1.2 V while occupying 5 mm × 5 mm in 0.13 μm CMOS. The interface offers simultaneous access to 96 channels of broadband neural data acquired from cortical microelectrodes as part of a head-mounted wireless recording system, enabling basic neuroscience as well as neuroprosthetics research. Signals are conditioned with a front-end achieving 2.2 μVrms input-referred noise in a 10 kHz bandwidth before conversion at 31.25 kSa/s by 10-bit SAR ADCs with 60.3 dB SNDR and 42 fJ/conv-step. Switched-capacitor filtering provides a well-controlled frequency response and utilizes windowed integrator sampling to mitigate noise aliasing, enhancing noise/power efficiency.

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This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several tens of millivolts

m CMOS

Giant magnetoresistive biosensors are becoming more prevalent for sensitive, quantifiable biomolecular detection. However, in order for magnetic biosensing to become competitive with current optical protein microarray technology, there is a need to increase the number of sensors while maintaining the high sensitivity and fast readout time characteristic of smaller arrays (1-8 sensors). In this paper, we present a circuit architecture scalable for larger sensor arrays (64 individually addressable sensors) while maintaining a high readout rate (scanning the entire array in less than 4s). The system utilizes both time domain multiplexing and frequency domain multiplexing in order to achieve this scan rate. For the implementation, we propose a new circuit architecture that does not use a classical Wheatstone bridge to measure the small change in resistance of the sensor. Instead, an architecture designed around a transimpedance amplifier is employed. A detailed analysis of this architecture including the noise, distortion, and potential sources of errors is presented, followed by a global optimization strategy for the entire system comprising the magnetic tags, sensors, and interface electronics. To demonstrate the sensitivity, quantifiable detection of two blindly spiked samples of unknown concentrations has been performed at concentrations below the limit of detection for the enzyme-linked immunosorbent assay. Lastly, the multiplexing capability and reproducibility of the system was demonstrated by simultaneously monitoring sensors functionalized with three unique proteins at different concentrations in real-time.

An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

The residue amplifiers in high-speed pipelined analog-to-digital converters (ADCs) typically determine the converters overall speed and power performance. We propose a mixed-signal technique that exploits incomplete settling to achieve low power residue amplification. In the first stage of a 12-bit, 75-MS/s proof-of-concept prototype, the employed open-loop residue amplifier dissipates only 2.9 mW from a 3-V supply, achieving >60% amplifier power reduction over a previously reported open-loop residue amplifier implementation and achieving >90% amplifier power reduction over a conventional opamp implementation. Test results show that the converters maximum signal-to-noise-and-distortion ratio (SNDR) is 65.6 dB. The measured integral and differential nonlinearity are 0.95 LSB and 0.64 LSB, respectively. The experimental chip occupies 7.9 mm2 and consumes 273 mW in a 0.35-mum double-poly, quadruple-metal CMOS process

GMR Biosensor Arrays: A System Perspective

This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.

A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and todays designs.