Brandon Eames

DesertFD: a finite-domain constraint based tool for design space exploration

As the complexity of computer based systems increases, designers are faced with the task of balancing a variety of design choices and parameters against conflicting optimization criteria. Design space exploration seeks to automate or partially automate the process of evaluating tradeoff decisions at design time. DesertFD is a domain-independent design space exploration tool which facilitates the representation and pruning of a design space using constraint satisfaction. DesertFD offers a formal tree-based view of a family of systems related through common structure, together with a flexible scripting language for modeling mathematical expressions governing property composition. User-specified constraints applied to the design space representation result in a pruning of the space. We discuss the reduction of the design space, property composition formulas and constraints into a constraint satisfaction problem using finite domain constraints. We examine two example design space exploration problems to evaluate DesertFD: the generation of a high level custom computer architecture for supporting H.264-based motion estimation, and the reliability-driven mapping of tasks to distributed embedded control units in a steer-by-wire automotive application.

Formalizing Functional Flow Block Diagrams Using Process Algebra and Metamodels

Functional flow block diagrams (FFBDs) are a traditional tool of systems engineering and remain popular in some systems engineering domains. However, their lack of formal definition makes FFBDs imprecise and impossible to rigorously analyze. The inability to analyze FFBDs may allow specification errors to remain undetected until well into the system design process or, worse, until the system is operational. To help address these problems, we have developed a precise formal syntax and semantics for FFBDs, based on the application of metamodels and the process algebra Communicating Sequential Processes (CSP). FFBDs constructed within our formalized framework are precisely defined and amenable to analyses of properties, such as safety, progress, and conformance to required scenarios. We demonstrate some of the analyses made possible by our formalization in a simple case study of system specification and show how our formalization can be used to detect and correct subtle system errors during the specification phase.

A Reconfigurable Load Balancing Architecture for Molecular Dynamics

This paper proposes a novel architecture supporting dynamic load balancing on an FPGA for a molecular dynamics algorithm. Load balancing is primarily achieved through the use of specialized processing units, referred to as FLEX units. FLEX units are able to switch between tasks required by a molecular dynamics algorithm as often as needed in order to cater to the nature of the input parameters. This architecture is capable of run-time performance analysis and dynamic resource allocation in order to maximize throughput. Results of a prototype of the architecture targeting an FPGA are presented.

Time-triggered buffers for event-based middleware systems

Application developers utilizing event-based middleware have sought to leverage domain-specific modeling for the advantages of intuitive specification, code synthesis, and support for design evolution. For legacy and cyber-physical systems, the use of event-based middleware may mean that changes in computational platform can result anomalous system behavior, due to the presence of implicit temporal dependencies. These anomalies are a function not of the component implementation, but of the model of computation employed for supporting system composition. In order to address these behavioral anomalies, the paper presents an approach where time-based blocks are inserted into the system to account for the temporal dependencies. An advantage of capturing the system composition in a domain-specific modeling language is the ability to efficiently refactor an application to include time-triggered, event-based schedulers. This paper describes how an existing event-based component topology can be modified to permit a time-triggered model of computation, with no changes to the existing component software. Further, the time-triggered components can be deployed alongside standard publish/subscribe methodologies. This strategy is beneficial to the maintenance of existing legacy systems upon upgrade, since the current operational mode could be maintained with minimal changes to the legacy software even under changes to the target platform which alter execution speed. These time-triggered layers are discussed in three permutations: fully triggered, start triggered, and release triggered. A discussion is provided regarding the limitations of each approach, and a brief example is given. The example shows how to apply these triggering approaches without the modification of existing components, but instead through the insertion of triggered buffers between legacy components.

Description of EduCOM: A graphical modeling and programming language for teaching and learning digital communication systems

This paper presents EduCOM, a graphical language for teaching and learning digital communication systems. In EduCOM students build graphical models (i.e., block diagrams) of digital communication transmitters, channels, and receivers. Then EduCOM creates the shell of a C/C++ code realization of the graphical model, but it leaves the implementation of each block empty so that students are required to implement the functionality of the blocks in a low‐level programming language such as C/C++. Therefore, EduCOM goes beyond passive drag–drop‐connect style activities and forces students to think more deeply about each operation performed on the signals in the system, and preliminary assessment results with a small set of students bear this point out. Students indicated that the mixture of graphical modeling and low‐level programming provided by EduCOM is an improvement over pure graphical modeling or pure low‐level programming in helping them learn about communication systems.

On the Use of DesertFD to Generate Custom Architectures for H.264 Motion Estimation

Deriving a custom architecture for H.264 video compression based motion estimation is a complex hardware design problem. The problem is complicated by the plethora of design options in the H.264 standard. To derive an efficient architecture, the designer must select between suitable algorithms, allocate computational resources to a custom datapath architecture, and schedule operations onto that architecture, while subject to constraints on both area and execution time. Design space exploration (DSE) addresses the design optimization problem by automating or semi-automating trade-off analysis. We use a DSE tool, DesertFD, to derive architectures for the motion estimation modules of a H.264 encoder. DesertFD is a domain- independent DSE tool which facilitates the representation and pruning of a design space using constraint satisfaction. Using post synthesis data for resource components, we use DesertFD to explore possible architectural solutions for H.264 motion estimation, subject to various area and latency constraints. Our results indicate that UMHEX algorithm is selected for tight area constraints while a five- step-search 5SS algorithm is selected otherwise.

A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs

The derivation of efficient, custom architectures for implementing algorithms on Field Programmable Gate Array platforms presents several research challenges. We focus on the derivation of efficient streaming architectures from dataflow graphs, targeting multi-cycle, fully pipelined functional units. In this paper, we present a Force-Directed Scheduling based algorithm for deriving area-efficient architectures from dataflow graphs based on replication and critical path relaxation. We have implemented this algorithm in a design tool called CHARGER, which integrates schedule generation with post-schedule communications infrastructure generation and Hardware Description Language generation. We compare the performance of our algorithm against that of a traditional Force-Directed Scheduling approach by generating architectures from algorithms selected from embedded computing and scientific computing.

Finite Domain Constraints Based Delay Aware Placement Tool for FPOAs

FPOAs are reconfigurable devices similar to FPGAs but offer a much higher level of abstraction than the gate level. The main advantage of FPOAs is their deterministic on chip network, which guarantees that an application executes at the design frequency. Mathstars current toolflow requires constant manual guidance to place and route a design. In this paper we propose a finite domain Constraint Satisfaction (CS) based approach, which considers the communication delay between hardware resources to ensure that they meet the designs timing requirement. We tested our Placement tool using a parameterized design test generator, and a 48-tap FIR filter. The tool reported a feasible solution for problems with known solutions, typically within a few seconds.

On the Use of DesertFD as a Reconfiguration Engine for Embedded Systems

Modern embedded systems dynamically interact with their environment. Certain classes of applications mandate drastic adaptation of runtime behavior in order to meet changes in system requirements. System reconfiguration involves dynamic changes to both the deployed algorithms and the allocation of system resources. In this paper we examine the use of a design space exploration tool, DesertFD, which utilizes constraint satisfaction to perform offline selection between various system configurations, as an online tool to facilitate dynamic exploration of the reconfiguration space. As a reconfiguration engine, DesertFD works well for classes of applications which require coarse-grained reconfiguration, or are tolerant to some amount of reconfiguration latency

On the Mitigation of MultiCore-Induced Behavioral Deviations of an Autonomous Ground Vehicle

Complex systems such as autonomous vehicles frequently utilize a distributed network of computers for sensing, control, and supervisory tasks. A common way to abstract the deployment of the computational nodes that implement the systems behavior is through the utilization of middleware, which treats each atomic processing element as a component. Multiple components may execute on a single node, and nodes are typically heterogeneous in their processing power. For component implementations that use an event-driven model of computation, however, significant behavioral deviations may occur when a single-core computational node is replaced with a multicore node, especially if that computational node is running more than one component. This paper discusses the observed behavioral deviations through a series of simulations with identical initial conditions, performed on various single core and multicore processing platforms. In addition to the empirical demonstration, the paper provides a technique to mitigate the behavioral deviations by inserting a time-triggered buffer between a key set of components, enforcing a loosely time-triggered execution even though the system is still defined through event-triggered components. This preserves existing legacy code, but provides a time-triggered execution.