Brent Gregory

ISIS: a system for performance driven resource sharing

The authors establish the importance of accurate bit-level area and delay modeling to the quality of circuits synthesized by resource sharing systems. They show that bit-level accuracy and integration with logic optimization are both desirable and feasible, since the added execution time is a small fraction of the total optimization time. The implementation of a resource sharing system called ISIS, which uses bit-level modeling, accounts for control delays, and optimizes sharing and resource performance selection together to generate high-quality circuits from register transfer language (RTL) descriptions, is described.<<ETX>>

Contributions from the “Best of ICCAD” to Synopsys

This paper highlights some examples of contributions from the selected ICCAD papers to Synopsys. We do not attempt to be exhaustive. Given the breadth of the topics addressed at ICCAD and the number of products offered by Synopsys this would be very difficult. We also try not to make any value judgments on the importance of a topic: In terms of (current) economic relevance markets speak for themselves, predicting future relevance accurately is impossible, and judgment on the technical relevance is subjective. So the given examples merely reflect the papers and products the authors are most familiar with. We hope however, that they do illustrate what it takes to create practical design technology (tools) starting from outstanding ideas.