Brian Donald Hart

Channel Bounding and MAC Protection Mechanisms for 802.11ac

In this paper, we investigate the problem of channel bounding in wireless local area networks (WLANs). We propose a MAC protection mechanism to combat the hidden node problem on non-primary channels of a basic service set (BSS). Simulation results show that the proposed MAC protection mechanism is effective in combating hidden nodes and improving throughput of 80MHz stations. The proposed scheme has been adopted into the IEEE 802.11ac specification as a mandatory feature. Furthermore, we extend the medium access mechanisms defined in 802.11n for a wider bandwidth, evaluate fairness of the 802.11n PIFS medium access mechanisms, and compare the performance of a dynamic bandwidth scheme with that of a static bandwidth implementation.

Advanced Wireless LAN Technologies: IEEE 802.11AC and Beyond

In 2013, global mobile data traffic grew 81% and it is projected to increase 11-fold between 2013 and 2018. Further, it is predicted that by 2018, over two-thirds of the worlds mobile traffic will be video and more than half of all traffic from wireless connected devices will be offloaded to Wi-Fi networks and femto-cells [1]. Consequently, wireless LANs need major upgrades to improve both throughput and efficiency. IEEE 802.11ac is an amendment to the 802.11 standard that was just ratified by IEEE 802.11. Promising up to gigabit data rates, many Wi-Fi products are being built based on this specification. In addition to technologies that improve throughput, IEEE 802.11ax is investigating and evaluating advanced wireless technologies that enable more efficient utilization of the existing spectrum.

A tri-mode 802.11 baseband PHY mixed signal integrated circuit in 0.13-μm CMOS

A 0.13um CMOS mixed signal 802.11a/b/g baseband PHY IC, with per-packet receive diversity, 802.11h radar/DFS support and an MRC/MIMO coprocessor interface, is described. Required receive C/N is 5dB at 6 Mbps, and 20dB at 54 Mbps. Residual packet error rate is less than 4% for 54 Mbps and 0.1% for 6 Mbps link data rates in a 50ns delay spread channel. The 4.75×4.75mm chip, fabricated in 1P7M 0.13um CMOS, has 8M transistors and dissipates under 31mW in sleep, 206mW in Tx, and 362mW in Rx.