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Dive into the research topics where Brian G. Moser is active.

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Featured researches published by Brian G. Moser.


compound semiconductor integrated circuit symposium | 2014

Analysis of the Influence of Layout and Technology Parameters on the Thermal Impedance of GaAs HBT/BiFET Using a Highly-Efficient Tool

Alessandro Magnani; V. d'Alessandro; Lorenzo Codecasa; Peter J. Zampardi; Brian G. Moser; N. Rinaldi

This work is focused on the analysis of the dynamic thermal behavior of advanced GaAs HBTs, with particular emphasis on BiFET technologies, where pHEMTs are integrated below the conventional bipolar device. A novel highly-efficient tool is employed to determine the influence on the thermal impedance of the key layout and technology features, namely, size of the emitter and base-collector mesa, pHEMT layers, and metallization architecture. The tool relies on the multi-point moment matching algorithm, and allows CPU time and memory storage much lower than those required by commercially-available numerical software packages.


Microelectronics Reliability | 2017

Simulation comparison of InGaP/GaAs HBT thermal performance in wire-bonding and flip-chip technologies

V. d'Alessandro; A. P. Catalano; Alessandro Magnani; Lorenzo Codecasa; N. Rinaldi; Brian G. Moser; Peter J. Zampardi

Abstract This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs for handset applications in a laminate (package) environment. Both wire-bonding and flip-chip technologies are examined. The combination between an accurate, yet fast, simulation capability and the Design of Experiments technique is employed to quantify the impact of all the key technology parameters and explore a wide range of operating conditions.


2015 Integrated Nonlinear Microwave and Millimetre-wave Circuits Workshop (INMMiC) | 2015

Technology comparison and considerations for handset power amplifiers

Peter J. Zampardi; Brian G. Moser

Average power power tracking (APT) and envelope tracking (ET) power amplifiers require high efficiency across a range of supply voltages, which is a change from old fixed voltage systems. The performance of these amplifiers is usually characterized by a so-called “waterfall curve”[1-3]. While circuit design choices can certainly be a factor in this roll-off of PAE with decreasing supply voltage, it is also necessary to evaluate device technologies to understand the trade-offs and opportunities they present for these applications. For technology development, it is advantageous to see if “simpler” measurements, such as RF-Knee[4] correlate to these waterfall measurements since they are easier to collect. In this paper, the considerations for device performance for these applications will be presented and discussed.


Archive | 2007

Integrated bipolar transistor and field effect transistor

Curtis A. Barratt; Michael T. Fresina; Brian G. Moser; Dain C. Miller; Walter A. Wohlmuth


Archive | 2012

GALLIUM ARSENIDE HETEROJUNCTION SEMICONDUCTOR STRUCTURE

Brian G. Moser; Michael T. Fresina


compound semiconductor integrated circuit symposium | 2015

Comparison of Technologies for APT and ET Applications

Brian G. Moser; Peter J. Zampardi; Marc Schulze Tenberge; Denny Limanto


Archive | 2015

HETEROJUNCTION BIPOLAR TRANSISTOR GEOMETRY FOR IMPROVED POWER AMPLIFIER PERFORMANCE

Brian G. Moser; Robert Saxer; Jing Zhang


compound semiconductor integrated circuit symposium | 2009

Modeling of an InGaP/GaAs BiFET VVR Device

William Clausen; Brian G. Moser


Archive | 2017

ADAPTIVE CAPACITORS WITH REDUCED VARIATION IN VALUE AND IN-LINE METHODS FOR MAKING SAME

Peter J. Zampardi; Brian G. Moser


Archive | 2017

ESD PROTECTION OF CAPACITORS USING LATERAL SURFACE SCHOTTKY DIODES

Peter J. Zampardi; Brian G. Moser; Michael Meeder; Venkata Chivukula

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Alessandro Magnani

Information Technology University

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N. Rinaldi

Information Technology University

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V. d'Alessandro

Information Technology University

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A. P. Catalano

Information Technology University

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