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Brian Gaudet

National Semiconductor

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Publication

Featured researches published by Brian Gaudet.

Archive | 1998

10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports

Brian Gaudet

Archive | 1999

Method and apparatus for adaptive equalization using feedback indicative of undercompensation

Brian Gaudet

Archive | 2000

Delay locked loop (DLL) based clock synthesis

Brian Gaudet

Archive | 2000

DLL calibrated switched current delay interpolator

Brian Gaudet

Archive | 2000

DLL calibrated phase multiplexer and interpolator

Brian Gaudet

Archive | 1998

High-speed network switch bus

Brian Gaudet; Vickie Sunnyvale Pagnon; Naveen Santa Clara Gopalakrishna

Archive | 1995

Scan flip-flop that holds state during shifting

Brian Gaudet; Rajendran Sharma; Ronald Pasqualini

Archive | 1998

High speed network switch bus clock

Brian Gaudet; Vickie Sunnyvale Pagnon

Archive | 2000

Apparatus and method to adaptively equalize duty cycle distortion

Brian Gaudet

Archive | 1998

Ground bounce control using DLL to optimize output stage di/dt using output driver replica

Brian Gaudet; Kristen Luttinger

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Vickie Sunnyvale Pagnon

National Semiconductor

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Naveen Santa Clara Gopalakrishna

National Semiconductor

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Kristen Luttinger

National Semiconductor

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Rajendran Sharma

National Semiconductor

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Ronald Pasqualini

National Semiconductor

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