Brian P. Railing

Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs

Parallel programs can be characterized by task graphs encoding instructions, memory accesses, and the parallel work’s dependencies, while representing any threading library and architecture. This article presents Contech, a high performance framework for generating dynamic task graphs from arbitrary parallel programs, and a novel representation enabling programmers and compiler optimizations to understand and exploit program aspects. The Contech framework supports a variety of languages (including C, C++, and Fortran), parallelization libraries, and ISAs (including × 86 and ARM). Running natively for collection speed and minimizing program perturbation, the instrumentation shows 4 × improvement over a Pin-based implementation on PARSEC and NAS benchmarks.

Extrapolation Pitfalls When Evaluating Limited Endurance Memory

Many new non-volatile memory technologies have been considered as a future scalable alternative to DRAM. Memory technologies such as MRAM, FeRAM, PCM have emerged as the most viable alternatives. But these memories have limited wear endurance. Practically realizable main memory systems employing these memory technologies are possible only if the wear across these memories is reduced as well as uniformly distributed. Limited endurance has resulted in extensive wear leveling research with the goal of uniformly distributing write traffic throughout available physical memory. Basic support for wear leveling is already present in existing systems, in the form of operating system paging. The Operating System (OS) changes virtual to physical translations over time. As a result, write traffic is naturally spread out. Proper evaluation of the need for wear leveling as well as the impact of the corresponding technique must take this phenomenon into account. Ignoring the effect of OS paging mechanism can result in highly inaccurate memory lifetime extrapolations. We demonstrate through simulation results, the effects of inaccurate extrapolations in the absence of OS modeling. Accurate memory lifetime simulation can take from many months to years. Although sampling techniques are commonly employed for speedup, our results show that naïve extrapolation techniques can lead to wildly different lifetime estimates. We show how sampling can be accurately applied by accounting for the different components in the write stream observed by main memory. Finally, we present a heuristic to quickly estimate memory lifetime for a given application.

Implementing Malloc: Students and Systems Programming

This work describes our experience in revising one of the major programming assignments for the second-year course Introduction to Computer Systems, in which students implement a version of the malloc memory allocator. The revisions involved fully supporting a 64-bit address space, promoting a more modern programming style, and creating a set of benchmarks and grading standards that provide an appropriate level of challenge. With this revised assignment, students were able to implement more sophisticated allocators than they had in the past, and they also achieved higher performance on the related questions on the final exam.

Active Learning in Systems Courses: (Abstract Only)

Research shows the benefit of using active learning in computer science education; however, only limited resources (such as, prior publications) exist for systems courses (including architecture, networking, operating systems). This BoF brings together practitioners of various levels of experience to discuss ways to augment or replace traditional lecturing. We will discuss different techniques, possible materials available, and results measured. This BoF should benefit both instructors considering adopting techniques and instructors looking to discuss issues with their usage.

Using Active Learning Techniques in Mixed Undergraduate / Graduate Courses (Abstract Only)

Active learning techniques are increasingly used in lower-level Computer Science courses. This work explores the use of active learning techniques in a graduate Computer Science course on computer architecture, where the course enrollment is composed of both undergraduates and graduate students. Initial results are presented on how the two groups of students respond differently to the techniques. In particular, the study includes the effect of using POGIL in place of a subset of lectures, measured through both student responses and test scores.