Bruce Andrew Doyle

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O

As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express®, DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be reduced further to 0.55ps upon switching to its auxiliary LC-VCO PLL (LC-PLL). As seen in Fig. 13.2.1, the clock system contains the two independent frequency synthesizers, an arrangement of programmable dividers to provide the required frequencies, and clock distribution circuitry. Furthermore, design-for-test features are embedded to correct for PVT variation for optimum jitter performance and to monitor PLL bandwidth and jitter peaking.

Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End

An alternating current (ac)-coupled high-speed receiver analog front end is capable of shifting the input direct current (dc) level without extra current consumption and signal degradation at high frequencies. However, the dc wander due to the high-pass characteristic of the ac-coupled front end may degrade the receiver performance because it equivalently modulates the sampling threshold voltage of the sampler. While this modulation may be negligible for highly dc-balanced input, it shows observable degradation in Peripheral Component Interconnect Express (PCIe) 3.0 receivers operating at 8 Gb/s. In addition, analog equalization is generally required for a PCIe 3.0 receiver front end. This paper presents techniques to add linear equalization and dc wander compensation into an ac-coupled receiver front end. The proposed linear equalization scheme attenuates the low-frequency energy and keeps the high-frequency energy. The proposed dc wander-compensation method is independent of process, voltage, and temperature; therefore, there is no need for calibration or compensation. The proposed schemes have very low power consumption and very good linearity because only passive and linear components are utilized in the main signal path. The proposed schemes were confirmed by simulation.

An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors

We present an 8.0-Gb/s HyperTransport source-synchronous I/O integrated in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design capping at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels by incorporating several jitter- and power-reduction enhancements. First, a high-bandwidth digital clean-up PLL is introduced to attenuate high-frequency jitter in the received forwarded clock before the data is sampled. This PLL achieves a highly programmable jitter bandwidth of 20-296 MHz (measured with 0.2 UIpp input jitter) and 0.90-1.50 ps output rms jitter by implementing an extended bang-bang phase detector for additional phase-error magnitude information and flexible bang-bang control of a current-starved ring-based oscillator. Second, several power-hungry circuits, namely the transmitter input FIFO and output driver as well as the receiver deserializer, are redesigned for 8.0-Gb/s operation to maintain thermal compatibility with the existing 45-nm socket package. The fabricated 20-lane I/O consumes 1.70 W at 8.0 Gb/s with an energy efficiency of 11.8 pJ/bit. This reflects a 4.9% increase in HyperTransport power consumption and only 0.3% increase in total processor target power relative to 45-nm operation at 6.4 Gb/s.

Loopback architecture for wafer-level at-speed testing of embedded HyperTransport TM processor links

We present transceiver serial loopback that enables cost-effective wafer-level at-speed testing of HyperTransportTM (HT) I/O for processor die-to-die communication. Besides facilitating known-good-die testing, this feature provides observability of multi-chip module (MCM) die-to-die links that are completely embedded without external pin visibility. We demonstrate production screening of 45-nm SOI-CMOS wafers at 6.4 Gb/s.

A High-Performance N-MOS Adder Designed for Optimized Cryogenic Operation

Low-temperature MOS devices (77 K) present significant gain in speed and density for a low technological cost. An N-MOS process has been adapted for use at liquid-nitrogen temperature using argon-implanted polysilicon resistors of very small dimensions as loads, instead of depleted devices. A ripple-carry 3-bit adder has been designed with 3- and 2.4-/spl mu/m roles to estimate the speed-power possibilities of the technology. It uses complex gates with quasi-static memorizing, and yields a maximum measured frequency of 405 MHz for a 28-mW power consumption, with 2.4-/spl mu/m design rules. This can be compared with results from the same circuit realized with other technologies (GaAs, 1-/spl mu/m N-MOS,/spl dot//spl dot//spl dot/).

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>200 MHz) PLL to attenuate high-frequency jitter in the received forwarded clock and redesigned power-hungry circuits to operate at 8.0 Gb/s within the existing 45-nm package thermal limit.