Bruce J. Currivan

An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution PLL, and digital image rejection. To our knowledge this is the first reported multichannel broadband tuner embedded in a DOCSIS 3.0 System on a chip implemented in 65 nm pure digital CMOS technology.

An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.

An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0

The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput can be obtained by bonding together multiple downstream (DS) channels. This standard calls for the ability to bond any 4 channels in a 64MHz contiguous RF bandwidth. Solutions that allow even more channel bonding and provide more flexibility in the allocated frequency spectrum are preferred. This paper reports an embedded dual-tuner architecture able to select two independent 32MHz frequency bands, allowing for a maximum of 10 demodulated 6MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0MHz (CH 0), +6MHz (CH +1), +12MHz (CH +2), −6MHz (CH −1) and −12MHz (CH −2). Channels +1 and +2 lie at the images of channels −1 and −2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.

A Full-Band processor for reduction of RF mixer LO harmonic images

A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50-1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm2 and uses 205 mW.