Bruce Wile

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional performance of the IBM POWER4 processor and the POWER4-based Regatta system. The approach was hierarchical, based on but considerably expanding the practice used for verification of the CMOS-based IBM S/390 Parallel Enterprise Server™ G4. For POWER4, verification began at the abstract, high-level design phase and continued throughout the designer and unit levels, the multi-unit level, and finally the multiple-chip system level. The abstract (high-level design) phase permitted early validation of the POWER4 processor design prior to its commitment to HDL. The designer and unit-level stages focused on ensuring the correctness of the microarchitectural components. Multiunitlevel verification, performed on storage and I/O components as well as on the processor, confirmed architectural compliance for each of the chips and subsystems. Finally, systemlevel verification tested multiprocessor coherence and system-level function, including processor-to-I/O communication and validation of multiple hardware configurations. In parallel with design and functional validation, verification of reliability functions, performance, and degraded configurations was also performed at most of the levels in the hierarchy.

Teaching future verification engineers: the forgotten side of logic design

This paper describes a senior/graduate level course in hardware logic verification being offered by The Ohio State University in cooperation with IBM. The need for the course is established through the growing importance of logic verification to users of custom logic designs. We discuss the short-term and long-term goals for the course, and describe the course content and format. The course relies heavily on lab projects to illustrate the main concepts. Three projects and a final project review are described.

Designer-level verification using TIMEDIAG/GENRAND

TIMEDIAG/GENRAND is a tool set used on various portions of the CMOS processor for the IBM S/390® Parallel Enterprise Server Generation 4 to assist in designer-level logic verification. The concept of surrounding the logic design (hereafter referred to simply as “logic”) under test with irritator behaviorals, a methodology developed and proven effective on larger simulation models, is moved to the designer level without the overhead of writing multiple behaviorals. Rather than writing source-level (e.g., VHDL, C code, etc.) behaviorals, the method creates an external stimulus to the design by using a series of generalized timing diagrams that obey the interface protocols of the logic under test. These timing diagrams are entered using the TIMEDIAG (timing diagram) editor. The effort required for logic verification is thus limited to understanding and laying out the interfaces to the design—a task that must be done for any well-designed unit of logic, regardless of whether or not it is being verified at the designer level. Once the timing diagrams are written, GENRAND (general random driver) is invoked to run simulation on the design. GENRAND randomly initiates the timing diagrams that obey the interface protocol, causing many different input and output permutations. This simulation is very effective in testing the logic implementation.

Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors

In this paper an approach is presented for thehierarchical verification of the memory control units, I/O adaptersand processor interconnect units as found in multiprocessorcomputer systems. It is shown how such units could be verifiedbetter and faster by the introduction of random executable timingdiagrams and associated CAD tool support. Furthermore, itis shown how the timing diagrams for the unit network verificationare easily derived from the timing diagrams specified for theunits. The multiprocessor hardware test showed the effectivenessof the proposed verification approach.