Bruno Kleinert

Competence research: teaching embedded micro/nano systems

In this paper, we present the development and first empirical refinement of a normative competence structure model for higher education in embedded micro systems and prospective embedded nanosystems. This kind of competence model is necessary to progress from a subjective and content oriented design of courses to traceable and outcome-oriented courses. In addition, we show a flexible alternative for teaching embedded systems in cost-intensive courses by building a FPGA laboratory offering remote access. Furthermore, we sketch out a possible way to overcome and teach fault-prone nanodevices in a Bottom-Up approach.

The empirically refined competence structure model for embedded micro- and nanosystems

Teaching the development of embedded micro- and nanosystems needs a well structured foundation. In this paper, we show how we refined our normative competence structure model (NCSM) to an empirical competence structure model (ECSM) by incorporating the results of a survey of German experts in the field of embedded systems. In addition, we introduce a course concept for a new internship which takes the results of the ECSM into account.

Competence model for embedded micro-and nanosystems

In this paper, we describe the results of an expert survey conducted within the project “Competence development with embedded micro- and nanosystems”. This survey was designed in order to refine our previously derived normative competence structure model for developers of embedded micro-and nanosystems towards an empirically refined competence structure model. Today the size of structural parts of nanosystems has scaled down to as few as a couple of molecules. This results in a lot of challenges regarding permanent and transient faults. Therefore bottom-up development techniques for nanostructured systems are now included into our competence model to prepare future developers to the specific challenges of designing at the nano scale. The evaluation of the content validity of the empirically refined competence structure model was accomplished by the presented expert rating.

Hardware-software co-simulation of self-organizing smart home networks: Who am I and where are the others?

In this paper, we present our solution to simulate home automation networks on a functional level in our research project on self-organizing home automation network nodes. We simulate the nodes with our hardware-software co-simulator, based on the virtual machine QEMU and the SystemC hardware simulator. The Virtual Distributed Ethernet suite is used to simulate several hardware-software co-simulators in a network. Furthermore, tools we developed to prepare network node disk images, configure the simulation environment, and generate Linux device drivers from hardware interface specifications are presented.

Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures

Performing a tsunami or storm surge simulation in real time on low power computation devices is a highly challenging research topic with a big impact on the lives of many people. In order to advance this topic further a tight collaboration between mathematics and computer science is needed. Mathematical models must be combined with numerical methods which, in turn, directly determine the computational performance and efficiency of the solution. Also, code parallelization is required in order to obtain accurate and fast simulation results. Traditional approaches in high performance computing require a lot of computational power and significant amounts of electrical energy; they are also highly dependent on uninterrupted access to a reliable network and power supply. We present a concept how to develop solutions for suitable low power hardware architectures for tsunami and storm surge simulations based on cooperative software and hardware simulation. The main goal is to enable in situ simulations on potentially battery-powered device on site. Flood warning systems in regions with weak or unreliable power, network and computing infrastructure could largely benefit from our approach as it would significantly decrease the risk of network or power failure during the computation.

Designing an OPC UA Based Ecosystem for Smarter Homes

The system architecture for self-organizing smart home ecosystems must fulfill the standard requirements of measuring home conditions, processing instrumented data, and monitoring home appliances as well as providing self-configurations mechanisms for the sensors and actors forming the ecosystem. The communication framework should allow devices to discover counterpart devices, discover the services they offers, invoke these services when needed and get notifications about the state changes of their cooperation partners. Our approach takes advantages of the communication framework OPC UA, since it provided a set of prebuild services, which can be adapted to our needs. The following lines describe the OPC UA communication framework first and describe the architecture of our communication model secondly.

Tsunami and Storm Surge Simulation Using Low Power Architectures

Performing a tsunami or storm surge simulation in real time is a highly challenging research topic that calls for a collaboration between mathematicians and computer scientists. One must combine mathematical models with numerical methods and rely on computational performance and code parallelization to produce accurate simulation results as fast as possible. The traditional modeling approaches require a lot of computing power and significant amounts of electrical energy; they are also highly dependent on uninterrupted access to a reliable power supply. This paper presents a concept how to develop suitable low power hardware architectures for tsunami and storm surge simulations based on cooperative software and hardware simulation. The main goal is to be able - if necessary - to perform simulations in-situ and battery-powered. For flood warning systems installed in regions with weak or unreliable power and computing infrastructure, this would significantly decrease the risk of failure at the most critical moments.