Bruno La Fontaine

Characterization of line-edge roughness in photoresist using an image fading technique

A technique was developed to investigate the role of aerial image contrast and image-log-slope (ILS) on the resulting magnitude of line edge roughness (LER) in resist with the goal of determining if the minimization of LER in current state-of-the-art, chemically amplified resist materials was limited by the quality of the projected aerial image or the materials and processing of the resist. The process of image fading was employed as the vehicle for controlled aerial image degradation. By reducing the quality of the aerial image through fading, the image contrast and ILS were decreased in a well-controlled and predictable manner, resulting in increased magnitude of LER. The link between experiment and simulation was made possible by the identification of the iso-fading condition, which in analogy to the iso-focal dose, results in a unique exposure dose for which the critical dimension (CD) of a resist feature does not change with increasing levels of fading. At the iso-fading condition, experimentally measured values for LER were analyzed as a function of the contrast and ILS of the aerial image used for patterning. It was determined that contrast was a poor predictor of the magnitude of LER though variations in feature type or illumination. The change in LER as a function of the ILS, however, produced a common basis for the comparison of LER through variations in line width, pitch, fading, increased background level of light, and illumination conditions. To include the effects of exposure dose on the resulting LER of resist features, the experimentally measured analog of the ILS, the resist edge-log-slope (RELS), was also used to produce a common curve for the evaluation of resist LER. Although overexposure can be used to further increase the ILS of the aerial image at the edge of the printed feature, the magnitude of 3σ LER in PAR735 resist appeared to be limited to a value of approximately 5.0nm in the limit of infinite RELS. This suggested that while the aerial image plays a strong role on determining the magnitude of LER during resist printing, there also exists a fundamental limitation to LER from the resist materials that cannot be improved by further increase in the quality of the aerial image.

Integration of EUV lithography in the fabrication of 22-nm node devices

On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices. In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination. The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level.

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

We describe methods to determine transfer functions for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying substrate. Both image fading techniques and more conventional focus-exposure matrix methods may be employed to determine the dependence of photoresist LER on the image-log-slope (ILS) or resist-edge-log-slope (RELS) of the aerial image. Post-etch LER measurements in polysilicon are similarly correlated to the ILS used to pattern the resist. From these two relationships, a transfer function may be derived to quantify the magnitude of LER that transfers into the polysilicon underlayer from the photoresist.1 A second transfer function may be derived from power spectral density (PSD) analysis of LER. This approach is desirable based on observations of pronounced etch smoothing of roughness in specific spatial frequency ranges. Smoothing functions and signal averaging of large numbers of line edges are required to partially compensate for large uncertainties in fast-Fourier transform derived PSDs of single line edges. An alternative and promising approach is to derive transfer functions from PSDs estimated using autoregressive algorithms.

The transfer of photoresist LER through etch

A method is presented to determine a transfer function for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying material, such as a polysilicon gate. The image fading technique was employed to determine the dependence of photoresist LER on the image-log-slope (ILS) of the aerial image. From this initial condition in resist, LER after the etch process was measured in polysilicon and related to the ILS used to pattern the resist. From these two relationships, a transfer function could be derived to quantify the magnitude of LER that transfers into the polysilicon under layer from the photoresist. A gate layer type film stack and a 193nm resist system were employed. Results demonstrated that photoresist LER did transfer through the etch process. Increasing the resist LER increased the post-etch LER in polysilicon, and accordingly, minimizing resist LER minimized polysilicon LER. The etch process can reduce the magnitude of roughness in polysilicon over a range of mid and low spatial frequencies, however the extent of the roughness reduction diminishes as the resist LER reaches its minimum at large values of the ILS. In addition, resist trim rates during etch were apparently increased when LER of the resist was large. These results demonstrate that post-etch LER in polysilicon may be limited by the minimum LER achievable in resist, despite the occurrence of apparent smoothing mechanisms through the etch process.

The SEMATECH Berkeley MET pushing EUV development beyond 22-nm half pitch

Microfield exposure tools (METs) play a crucial role in the development of extreme ultraviolet (EUV) resists and masks. One of these tools is the SEMATECH Berkeley 0.3 numerical aperture (NA) MET. Using conventional illumination this tool is limited to approximately 22-nm half pitch resolution. However, resolution enhancement techniques have been used to push the patterning capabilities of this tool to half pitches of 18 nm and below. This resolution was achieved in a new imageable hardmask which also supports contact printing down to 22 nm with conventional illumination. Along with resolution, line-edge roughness is another crucial hurdle facing EUV resists. Much of the resist LER, however, can be attributed to the mask. We have shown that intenssionally aggressive mask cleaning on an older generation mask causes correlated LER in photoresist to increase from 3.4 nm to 4.0 nm. We have also shown that new generation EUV masks (100 pm of substrate roughness) can achieve correlated LER values of 1.1 nm, a 3× improvement over the correlated LER of older generation EUV masks (230 pm of substrate roughness). Finally, a 0.5-NA MET has been proposed that will address the needs of EUV development at the 16-nm node and beyond. The tool will support an ultimate resolution of 8 nm half-pitch and generalized printing using conventional illumination down to 12 nm half pitch.

EUV lithography at the 22nm technology node

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because we believe that device integration exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the 0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

Investigation of the Current Resolution Limits of Advanced Extreme Ultraviolet (EUV) Resists

The past two years has brought tremendous improvements in the crucial area of resists for extreme ultraviolet (EUV) lithography. Nested and isolated line resolutions approaching 30 nm and 25 nm, respectively, have been demonstrated. These advances have been enabled, in large part, by the high-numerical (0.3) EUV imaging capabilities provided by the Berkeley microfield exposure tool (MET). Here we investigate the resolution limits in several advanced EUV resists using the Berkeley MET. Comparisons to aerial-image performance and the use of resolution-enhancing illumination conditions are used to establish the fact that the observed pattern resolution in the best chemically-amplified resists available today are indeed resist limited. Moreover, contrast transfer function (CTF) techniques are used to directly compare various advanced resists. Strong correlation is observed between relative CTF performance and observed resolution limits.

Laser produced plasma EUV sources for device development and HVM

Laser produced plasma (LPP) systems have been developed as the primary approach for the EUV scanner light source for optical imaging of circuit features at sub-22nm and beyond nodes on the ITRS roadmap. This paper provides a review of development progress and productization status for LPP extreme-ultra-violet (EUV) sources with performance goals targeted to meet specific requirements from leading scanner manufacturers. We present the latest results on exposure power generation, collection, and clean transmission of EUV through the intermediate focus. Semiconductor industry standards for reliability and source availability data are provided. We report on measurements taken using a 5sr normal incidence collector on a production system. The lifetime of the collector mirror is a critical parameter in the development of extreme ultra-violet LPP lithography sources. Deposition of target material as well as sputtering or implantation of incident particles can reduce the reflectivity of the mirror coating during exposure. Debris mitigation techniques are used to inhibit damage from occuring, the protection results of these techniques will be shown over multi-100s of hours.

Architectural choices for EUV lithography masks: patterned absorbers and patterned reflectors

Photoresist patterning experiments on the EUVL Engineering Test Stand using two masks with different types of architecture indicate that etched-multilayer binary masks can provide larger process latitude than standard patterned absorber masks. The trends observed in the experimental data are confirmed by rigorous electromagnetic simulations taking into account the mask structure, the imaging optics characteristics and the illumination conditions.

Laser produced plasma EUV light source for EUVL patterning at 20nm node and beyond

This paper describes the development of a laser-produced-plasma (LPP) extreme-ultraviolet (EUV) source for advanced lithography applications in high volume manufacturing. EUV lithography is expected to succeed 193nm immersion double patterning technology for sub-20nm critical layer patterning. In this paper we discuss the most recent results from high power testing on our development systems in San Diego, and describe the requirements and technical challenges related to successful implementation of these technologies. Subsystem performance will be shown including the CO2 drive laser, droplet generation, laser-to-droplet targeting control, intermediate-focus (IF) metrology, out-of-band (OOB) radiation measurements and system use and experience. In addition, a multitude of smaller lab-scale experimental systems have also been constructed and tested..