Bruno Stefanelli

An All-Digital RF Signal Generator Using High-Speed

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm2 (0.15 mm2 for the active area).

\Delta\Sigma

A mixed-signal integrated circuit implements 1120 analog memory points arranged in 16 independent fully programmable delay lines in a 0.8 /spl mu/m CMOS technology. It demonstrates the feasibility of large scale mixed-mode circuits using the switched current technique. The die area of the chip is 72 mm/sup 2/ and incorporates 16 rather large and complex analog blocks, which take advantage of special design techniques developed in order to keep power consumption at a reasonable level and to eliminate second-order effects due to long power and signal lines. At the nominal 64 MHz sampling rate, harmonic distortion is -48 dB, dynamic range is above 60 dB, and power consumption is 1.22 W from a single 5 V supply.

Modulators

A fifth-order elliptic low-pass continuous-time filter based on triode transconductors for applications in the video frequency range is presented. Fabricated in a standard 2- mu m CMOS technology, the circuit occupies 6 mm/sup 2/ of silicon area including the automatic tuning circuitry. The filter achieves a 7-MHz cutoff frequency using a parasitic pole compensation scheme. The dynamic range is 40 dB and power consumption is 30 mW for a 5-V supply. A transconductor biasing strategy which allows a continuous tuning range for the cutoff frequency of one decade is presented. >

An analog beam-forming circuit for ultrasound imaging using switched-current delay lines

A CMOS preamplifier optimized for piezoelectric transducers is presented. The extensive use of CMOS-compatible lateral bipolar transistors (CLBTs) and careful layout leads to a very low noise along with good untrimmed DC and AC characteristics. These features make it competitive with bipolar and JFET realizations. In addition, long coaxial lines can be driven without significant alteration of performance using the two uncommitted on-chip buffers. This circuit was fabricated in a standard 3- mu m p-well CMOS technology, opening perspectives to monolithic integration of data acquisition subsystems. >

A 2- mu m CMOS fifth-order low-pass continuous-time filter for video-frequency applications

This paper presents a very high-speed delta-sigma modulator for achieving digital generation of radio-frequency signals. About 68 dB of ACLR (adjacent channel leakage ratio) is obtained on the 7.8 GS/s output of the delta-sigma modulator for WCDMA standard. This is achieved by using original concepts like borrow-save arithmetic, non-exact quantization and differential dynamic logic.

A very low-noise CMOS preamplifier for capacitive sensors

This paper presents a reconfigurable semi-digital RFFIR filter suitable for digital transmitters using 1-bit DeltaSigma signal generation. A transmission line based 5-channel power combiner allows both increase of output power and programmable filtering of the signal. A prototype has been built with 65 nm CMOS and Integrated Passive Devices (IPD) technologies. The system exhibits a 14 dB power gain for a peak power of 17 dBm at 1.2 GHz and an attenuation of out-of band noise of up to 15 dB. CMOS and IPD chip size are respectively 2.05 mm2 and 17.78 mm2.

Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RE transmitters

This paper presents the design and measurement of a 4 × oversampled 18th order digital low-pass FIR filter. It is a key building block in the proposed digitally enhanced transmitter architecture for 60 GHz wireless high-data rate links. Spectrum mask requirements are fully satisfied for OFDM modulated signals without requiring additional analog filtering. Pipelined CPL adders and TSPC flip-flops are used to enable a very high operation frequency. The core area is 0.1 mm2 in a standard GP 65 nm CMOS process. Measured power consumption is 400 mW at 9.6 GS/s with a 1.4 V power supply voltage.

A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner

Digital generation of radio-frequency signals is a key concept of software defined radios. This paper presents a digital transmitter chain including a very high-speed delta-sigma modulator. It comprises also baseband processing, sample rate conversion, digital upconverter and output stages (switching- mode amplifier and BAW filters). About 74 dB of ACLR (adjacent channel leakage ratio) is obtained on the 7.8 GS/s output of the delta-sigma modulator for the WCDMA standard.

A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters

The presented digital RF signal generator in 90 nm CMOS uses 1-bit DeltaSigma modulation and targets mobile communication terminals. A 50 MHz bandwidth centered on 1 GHz can be achieved when the circuit is clocked at 4 GHz. Signals up to 3 GHz can be synthesized when using the first image band. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. The digital core employs redundant arithmetic, precomputed non-exact quantization and differential dynamic logic. The digital core consumes 49 mW at maximum clock frequency. Active area is 0.15 mm2.

All-digital RF signal generation for software defined radio

This paper summarizes research towards the realization of a fully-integrated, compact, intelligent MEMS (Smart MEMS). The system performs the cooperative function of microactuators by integration with sensors and processors. By using a cooperative operation the weak force of each microactuator is gathered so the system can produce a strong force, in preserving the precise motion control thanks to the high resonant frequency of microactuators and short feedback cycle of the integrated processor. The design of a demonstration system is presented in this paper.