Bui Nguyen Quoc Trinh

A low-temperature crystallization path for device-quality ferroelectric films

We show a path for low-temperature crystallization of device-quality solution-processed lead zirconate titanate films. The essential aspect of the path is to circumvent pyrochlore formation at around 300 °C during temperature increase up to 400 °C. By maintaining enough carbon via pyrolysis at 210 °C, well below the temperature for pyrochlore formation, Pb2+ can be reduced to Pb0. This leads to the lack of Pb2+ in the film to suppress the development of pyrochlore, which accounts for the usual high-temperature conversion to perovskite. Films on metal, metal/oxide hybrid, and oxide bottom electrodes were successfully crystallized at 400–450 °C.

Totally solution-processed ferroelectric-gate thin-film transistor

We have fabricated inorganic ferroelectric-gate thin film transistors (FGTs) using only a chemical solution deposition (CSD) process. All layers, including the channel [indium-tin-oxide (ITO)], ferroelectric-gate insulator [Pb(Zr,Ti)O3], gate electrode (LaNiO3) and source/drain electrodes (ITO), were formed by the CSD process. The fabricated FGT exhibited typical n-channel transistor operation with good saturation in drain current and drain voltage (ID-VD) characteristics. The obtained on/off current ratio, memory window, and subthreshold voltage swing were about 107, 2.5 V, and 420 mV/decade, respectively.

Ferroelectric-Gate Thin-Film Transistor Fabricated by Total Solution Deposition Process

We have fabricated inorganic ferroelectric-gate thin-film transistors (FGTs) using only a chemical solution deposition (CSD) process. All layers, including the LaNiO3 (LNO) gate electrode, Pb(Zr,Ti)O3 (PZT) ferroelectric-gate insulator, indium–tin-oxide (ITO) source/drain electrodes, and ITO channel, were formed on a SrTiO3 (STO) substrate by the CSD process. We obtained a local epitaxially grown PZT/LNO perovskite heterostructure with good crystalline quality and no interfacial layer. The fabricated FGT exhibited typical n-channel transistor operation, with a counterclockwise hysteresis loop due to the ferroelectric nature of the PZT-gate insulator, and also exhibited good drain current saturation in output characteristics. These properties are equivalent to or better than those obtained with FGTs fabricated by means of conventional vacuum processes. The obtained on/off current ratio, memory window, and subthreshold voltage swing were about 106, 2.5 V, and 357 mV/decade, respectively.

Optimization of Pt and PZT Films for Ferroelectric-Gate Thin Film Transistors

The polycrystalline Pt film with an excellent (111) orientation and a small grain size of about 30 nm was successfully prepared on a SiO2/Si substrate by the new structured-sputtering system. By optimizing annealing process and using the highly (111)-oriented Pt film as a bottom electrode, an epitaxial-grade (111)-oriented PZT film was successfully prepared by the sol-gel method. Operation of the ferroelectric-gate thin film transistor (FGT) with indium-tin-oxide (ITO) channel, which was based on the optimum Pt and PZT films, has been verified. The FGT device exhibited good properties and performance with high “on/off” current ratio (∼105), adequate memory window (1.2 V) and small swing factor (∼88 mV/decade).

Interface Charge Trap Density of Solution Processed Ferroelectric Gate Thin Film Transistor Using ITO/PZT/Pt Structure

The conductance method was applied to investigate the interface charge trap density (Dit ) of solution processed ferroelectric gate thin film transistor (FGT) using indium-tin oxide (ITO)/ Pb(Zr,Ti)O3 (PZT)/Pt structure. As a result, a large value of Dit of MFS capacitor, i.e., Pt/PZT/ITO, was estimated to be 1.2 × 1014 eV−1 cm−2. This large Dit means that an interface between the ITO layer and the PZT layer is imperfect and it is one of the main reasons for the poor memory property of this FGT. By using transmission electron microscopy (TEM), this imperfect interface was clearly observed. Thus, it is concluded that improvement of this interface is critical for better memory performance.

Fabrication of 120-nm-channel-length ferroelectric-gate thin-film transistor by nanoimprint lithography

Nanoimprint lithography (NIL) is one of the most promising device fabrication techniques because it has a high resolution and moderate fabrication cost. Oxide-based thin-film transistors (TFTs) with various physical properties have the potential to outperform Si-based large-scale integration (LSI) devices. In this study, we focus on the miniaturization of oxide-based TFTs by NIL. A ferroelectric-gate thin-film transistor (FGT) was prepared by incorporating a chemical-solution-deposition (CSD)-processed indium tin oxide channel, a Pb(Zr,Ti)O3 (PZT) gate insulator, and sputtered Pt electrodes. The Pt source?drain electrodes and ITO channel were patterned by the NIL process. The results show that we successfully fabricated an FGT with a channel length of 120 nm by NIL. The 120 nm channel length was confirmed by scanning electron microscopy (SEM). The fabricated NIL-FGT showed typical n-channel transistor characteristics. The obtained ON/OFF current ratio, threshold voltage, subthreshold voltage, and field-effect mobility were 103, 0.5 V, 1.0 V/decade, and 0.1?0.2 cm2?V?1?s?1, respectively.

Fabrication and characterization of a ferroelectric-gate FET With a ITO/PZT/SRO/Pt stacked structure

We have demonstrated nonvolatile memory operation of a ferroelectric-gate thin film transistor (FGT) using solution-processed indium-tin-oxide (ITO) as a channel layer with combination of a PZT/SrRuO3/Pt gate stacked structure. A well-defined ITO/PZT interface with atomically flat PZT surface and a negligibly compositional interdiffusion were obtained, which indicate that the use of a SrRuO3 (SRO) buffer layer between Pt and PZT provides a homogeneous crystal orientation as well as stable perovskite structure for PZT. Furthermore, the fabricated FGT exhibits a high “ON/OFF” current ratio (ION/IOFF) of 106 and a large memory window of 2.5 V. Such a high current ratio is due to large carrier modulation induced by ferroelectricity of PZT. This device with excellent operation can be a good candidate for nonvolatile memory applications.

Electric Properties and Interface Charge Trap Density of Ferroelectric Gate Thin Film Transistor Using (Bi,La)4Ti3O12/Pb(Zr,Ti)O3 Stacked Gate Insulator

6, a large memory window of 1.7–3.1V, and a large ON current of 0.5–2.5mA. In order to investigate interface charge trapping for these devices, we applied the conductance method to MFS capacitors, i.e., Pt/ITO/BLT/PZT/Pt capacitors. As a result, the interface charge trap density (Dit) between the ITO and BLT/PZT stacked films was estimated to be in the range of 10 11 –10 12 eV 1 cm 2 . The small Dit value suggested that good interfaces were achieved.

Sub-100 nm Ferroelectric-Gate Thin-Film Transistor with Low-Temperature PZT Fabricated on SiO2/Si Substrate

Thin film transistor which uses an active oxide-semiconductor channel and a ferroelectric-gate insulator, so-called FGT, has wide attention for the application of a new nonvolatile memory owing to its prominent features such as simple structure, high speed and low power consumption. Previously, we have reported on demonstration of the FGTs operation, but the ones developed have channel lengths (LDS) more than 100 nm, which should be reduced for high-density storage in integration circuits. In this work, a new technique has been proposed to fabricate the sub-100 nm FGT using low-temperature PZT thin film, whose source-drain gap would be mainly created from electron beam lithography, dry etching and ashing. With the new technique, the memory functionality of the fabricated sub-100 nm FGTs are comparable with that of the sub-μm sized FGT. In particular, the ON/OFF current ratio is about 104–105, the memory window is 2.0, 1.8 and 1.7 V, and the field-effect mobility is 0.12, 0.07 and 0.16 cm2V−1s−1 for the LDS of 100, 50, and 30 nm, respectively.

Data Disturbance-free NAND-type Ferroelectric-gate Thin Film Transistor Array using Solution-processed ITO and Stacked (BLT/PZT) Gate Insulator

We have proposed and fabricated NAND memory array using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed by a sol-gel ITO channel and a sol-gel stacked ferroelectric (BLT/PZT) gate insulator. We verified almost data disturbance-free operation with a small loss of the memory state.