Bum-Seok Suh

A novel PWM scheme for a three-level voltage source inverter with GTO thyristors

This paper presents a new PWM scheme for a three-level GTO inverters based on space voltage vectors. By this PWM method, the harmonic components of the output voltage can be minimised by avoiding the minimum pulse width limitation problem of the GTO and voltage balancing of DC link capacitors can also be kept. The principle of the PWM method and the voltage vector selection procedure are described in detail. Computer simulation and experimental results verify that the proposed PWM control scheme is suitable for high power and high voltage three-level GTO inverters applied to induction motor drives.<<ETX>>

A new n-level high voltage inversion system

This paper deals with a new multilevel high-voltage source inverter with gate-turn-off (GTO) thyristors. Recently, a multilevel approach seemed to be the best suited for implementing high-voltage power conversion systems because it leads to a harmonic reduction and deals with safe high-power conversion systems independent of the dynamic switching characteristics of each power semiconductor device. A conventional multilevel inverter has some problems; voltage unbalance between DC-link capacitors and larger blocking voltage across the inner switching devices. To solve these problems, the novel multilevel inverter structure is proposed.

An improved carrierwave-based SVPWM method using phase voltage redundancies for generalized cascaded multilevel inverter topology

Carrierwave-based space vector pulse width modulation (SVPWM), which is considered as a highly simple and efficient PWM technology, can be also used in multilevel inverters. The method was originally designed for the two-level inverter and developed to the diode-clamped multilevel inverter structure. However it may be noted that it also causes bad switch utilization in cascaded multilevel inverters. This paper introduces an improved carrierwave-based SVPWM scheme, which is fully compliant with cascaded inverter topologies because it can achieve the optimized switch utilization using phase voltage redundancies while having the advantages of the conventional carrierwave-based SVPWM. Using experimental results, the superior performance of a new PWM method is shown.

Design consideration for the improved Class-D inverter topology

The characteristics and the superiority of the efficient snubber network for Class-D series resonant inverters are addressed in detail by comparison with conventional snubbers, i.e., the lossless capacitive snubber and the RC snubber, with respect to switching losses, overvoltage stresses, high-frequency resonant current stresses, and overall efficiency. Also, the optimal design scheme for it is considered and the analytical equations are derived in order to provide a straightforward and easy-to-design tool. The validity of the theoretical description is verified by testing on a 29-kHz MOSFET Class-D series resonant inverter rated at 1.2 kW.

A new class-D voltage source series-loaded resonant inverter topology considering stray inductance influences

A new class-D voltage source series-loaded resonant inverter topology which can reduce the influences of the stray inductance is proposed. In the conventional class-D inverter topology, the stray inductance not only results in an overvoltage which gives the voltage stresses to the switches, but also in high frequency resonant currents during the turnoff transients. The proposed class-D inverter is superior to the conventional class-D inverter with respect to the reduction of problems due to the stray inductance. It is also more suitable for high power and high frequency inverters. The characteristics and the validity of the proposed class-D inverter are verified by both simulation and experimental results.

A new snubber circuit for high efficiency and overvoltage limitation in three-level GTO inverters

A new low loss snubber circuit including overvoltage clamping circuit for a three-level GTO inverter is presented. The proposed snubber circuit is effective in the restriction of the dv/dt and the overvoltage values across each GTO at turn-off and the snubber loss is less than the half that of the conventional RCD snubber circuit. In addition, there is no blocking voltage balancing problem between the inner and the outer GTOs that occurs in the case when a conventional RCD snubber circuit is used in a three-level inverter topology. Experimental results demonstrate that the proposed snubber circuit is very effective for a large capacity three-level GTO inverter.

A new gate drive circuit for high-speed operation of GTO thyristors

This paper presents a new gate turn-off drive circuit for GTO thyristors, which can accomplish faster turn-off switching for high-speed operation of the GTO. The switching characteristics of GTOs can be improved by use of the gate drive circuit that is able to make a very high rate of the negative gate current. The major disadvantage of the conventional gate turn-off driving technique is that it has a difficulty in realizing higher negative di/sub G//dt due to the maximum reverse gate-cathode voltage and the stray inductances within the gate turn-off drive circuit. This paper shows that this problem can be overcome by adding another gate turn-off drive circuit to the conventional gate turn-off drive circuit. Simulation and experimental results in conjunction with chopper circuit verify the performance of the proposed gate drive circuit. >

Design considerations for the improved Class-D inverter topology

The characteristics of the improved Class-D inverter and its optimal design considerations are described. Analytical considerations and equations are presented to provide easy-to-use design tools. A theoretical description for the design of the turn-off snubber capacitor, the overvoltage clamping snubber capacitor, and the damping resistors is explained. The validity of the theoretical description is verified by experimental results.