Buyeol Lee

Color moiré simulations in contact-type 3-D displays.

A new method of color moiré fringe simulation in the contact-type 3-D displays is introduced. The method allows simulating color moirés appearing in the displays, which cannot be approximated by conventional cosine approximation of a line grating. The color moirés are mainly introduced by the line width of the boundary lines between the elemental optics in and plate thickness of viewing zone forming optics. This is because the lines are hiding some parts of pixels under the viewing zone forming optics, and the plate thickness induces a virtual contraction of the pixels. The simulated color moiré fringes are closely matched with those appearing at the displays.

Numerical simulation of the displayed image on the entire screen of autostereoscopic displays

A three-dimensional simulation model calculating the optical intensity distribution for the entire screen of an autostereoscopic display at a given eye position was developed in this study. A parallax barrier array was used for the optical model and reverse ray tracing of light from the observers eye to the subpixels through the slits of the barrier was performed based on reverse geometrical optics. By investigating the optical behavior of the displayed image for the nine-view design condition for various viewing distances, we found the inhomogeneous crosstalk from the unwanted views and predicted segmented images which were comprised of multiple images from different views on the entire display screen. From the results, our simulation model shows good potentiality for predicting the displayed image on the entire display screen of autostereoscopic displays for various positions of the observers eye with sufficient calculation speed.

6.3: A Low‐EMI 2Gbps ClockAlignedtoData IntraPanel Interface (CADI) for TFT‐LCD with the VSYNC‐Embedded Clock and Equalization

A pointtopoint intrapanel interface for data and clock of TFT LCD in 0.18um works at 2Gbps, with the 10∼20dB EMI enhancement over the clock embedding scheme. The subpixel clock is cascaded with the transition time maximized for low EMI. The VSYNC is embedded in the clock. DLL aligns clock and data.

High-performance speech recognition for TVs with NLMS and beamforming

In order to remove TV noise effectively, a novel system, combination of single channel and multi-channel microphone-based noise reduction method, is proposed. A single channel filtering based on normalized least mean square is performed on each channel to reduce TV noise using a reference noise provided by TV speaker output. After that, as a post-processing, generalized sidelobe canceller attenuates more the remaining nonstationary noises in input speeches. For performance evaluation, a HMM-based speaker recognition rate is measured and the recognition rate showed remarkable improvement.

40.4: Invited Paper: iDP Standard for an Internal Connection in a Large‐screen Display

This paper provides for a technical overview of iDP (Internal DisplayPort) Standard Ver. 1.0. The iDP is an open industry standard developed for transporting a video pixel stream from a TV/monitor controller SOC (system on chip) to a TV/monitor panel TCON within a TV/monitor chassis. This standard leverages the proven DisplayPort technology at its simplest form. Targeted at replacing LVDS, the iDP consists of Main Link and HPD signal, operating without sideband channel. Instead of AUX CH of DisplayPort Standard, the iDP uses HPD pulse to coordinate Link Training; an iDP sink device asserts an HPD pulse to prompt an iDP source device to transmit Link Training patterns over Main Link. Nominal iDP link rate of 3.24Gbps/lane enables the transport of FHD240Hz video stream with the pixel bit depth of 30 bits per pixel over 8 lanes (or differential pairs), as opposed to 48 differential pairs of Quad LVDS link. The permitted number of lanes per bank k 1 to 16 lanes inclusive, and the permitted number of banks k 1 or more, depending on a panel configuration. Using data throttling technique, an iDP source device enables an iDP sink device to regenerate the pixel clock synchronously from a link symbol clock as in f_pixel_clock = f_LinkSymbolClock * Mvid /48, where Mvid is an 8-bit integer value, thus allowing for further simplification of an iDP TCON implementation.