Byongsu Seol

Software-based analysis of the effects of electrostatic discharge on embedded systems

This paper illustrates the use of software for monitoring and recording the effects of electrostatic discharge (ESD) on the operation of embedded systems, with the goal of facilitating root-cause analysis of resulting failures. Hardware -- based scanning techniques are typically used for analyzing the effect of ESD on systems by identifying physical coupling paths. This paper proposes software techniques that monitor registers and flags associated with peripherals of embedded systems to detect faults associated with the effects of ESD. A lightweight, cost-effective, and non-intrusive software tool has been developed that monitors and records the status of all registers associated with a designated peripheral under test, identifying the fault propagation caused by ESD in the system, and visually presenting the resulting errors. The tool has been used to detect and visually summarize ESD-induced errors on the SD card peripheral of the S3C2440 development board, using local injection and system-level scanning. Root-cause analysis of these faults can potentially assist in identification of coupling paths of electromagnetic interference, as well as determination of areas of the hardware that are more vulnerable to ESD.

Efficient Calculation of Inductive and Capacitive Coupling Due to Electrostatic Discharge (ESD) Using PEEC Method

The coupling from electrostatic discharge (ESD) events is effectively calculated using the partial element equivalent circuit (PEEC) method, both in time and frequency domains. The PEEC method has several advantages in predicting dominant coupling sources and waveforms of ESD. Two victim structures were designed so that the inductive or capacitive coupling could be dominant. The calculation of ESD coupling is validated by comparison with measurements and the finite-element method solver in frequency domain. The waveform of the ESD inductive coupling is also validated with measurements and the finite-difference time domain solver in time domain.

Measurement of discharging currents through an IC due to the charged board event using a shielded Rogowski coil

The discharging currents through an IC induced by the charged board event (CBE) is measured using a shielded Rogowski coil. Several shielding techniques are applied in the measurement to reduce the common mode noise and the unexpected electric field coupling. The measured results are validated with the CBE circuit simulations.

Fast calculation of system-level ESD noise coupling to a microstrip line using PEEC method

The system-level ESD coupling on a microstrip line is calculated using the partial element equivalent circuit (PEEC) method both in frequency and time domains. A simplified MNA matrix for the victim trace is proposed to quickly calculate the charge and current induced due to the ESD event. The calculated coupling transfer impedance and the ESD waveforms coupled on the traces are validated by comparison with measurements both in frequency and time domains.

Efficient calculation of ESD inductive coupling on a conductor loop using PEEC method

The transient voltage waveforms coupled by ESD events are effectively calculated using the partial element equivalent circuit (PEEC) method. The PEEC method has several advantages in prediction of ESD transient waveforms. As a test, a victim structure has been designed for the inductive coupling to be dominant. The calculated waveforms are validated by comparison with measurements both in frequency and time domains.

System-Level Modeling Methodology of ESD Cable Discharge to Ethernet Transceiver Through Magnetics

When a charged cable is plugged into an Ethernet connector, a cable discharge event (CDE) will occur. Ethernet transceiver pins are often affected by CDE as they are usually unshielded. The discharge current couples via the transformer and common mode chokes to the physical layer-integrated circuit and may damage it. This paper describes a methodology for CDE system-level modeling in SPICE taking the cable geometry into account via full-wave modeling and cross-sectional analysis. A charged cable model, a nonlinear magnetics model, an Ethernet transceiver pin model, and the traces in the system are combined to create a complete model. An Ethernet system suffering cable discharge was selected to illustrate the methodology. The simulation is compared to measurements.

Software-Based Instrumentation for Localization of Faults Caused by Electrostatic Discharge

Electrostatic discharge (ESD) is often the cause of system-level failure or malfunction of embedded systems. The underlying faults are difficult to localize, as the information gained from the hardware-based diagnostic methods typically in use lacks sufficient detail. The alternative proposed in this paper is software instrumentation that monitors key registers and flags to detect anomalies indicative of failure. In contrast to hardware-based techniques, which use invasive probes that can alter the very phenomena being studied, the proposed approach makes use of standard peripherals such as the serial or Ethernet port to monitor and record the effect of ESD. We illustrate the use of this software instrumentation technique in conjunction with a three-dimensional ESD injection system to produce a sensitivity map that visualizes the susceptibility of various segments of an embedded system to ESD.

System-level ESD noise induced by secondary discharges at voltage suppressor devices in a mobile product

The system-level ESD noises induced by a secondary discharge at voltage suppressor devices in a mobile product are measured and analyzed. Two kinds of voltage suppressor devices, voltage clamping-type and snapback-type devices, are characterized using TLP measurements. The voltage waveforms at the voltage suppressor devices and the power-ground decoupling capacitors are measured and analyzed according to several kinds of voltage suppressor devices.

Fast and Accurate Calculation of System-Level ESD Noise Coupling to a Signal Trace by PEEC Model Decomposition

A fast and accurate calculation method of system-level electrostatic discharge (ESD) noise coupling based on model decomposition of the partial element equivalent circuit is proposed. The proposed method can significantly reduce the calculation time without loss of accuracy by separating small victim signal traces from large aggressor structures such as ground planes and ESD gun strap. Using the method, the ESD noise coupling at the terminations of a victim signal trace is rigorously calculated and validated with measurements and full-wave simulations in both frequency and time domains.

IC Failure Analysis Due to Charged Board Events by Measurements and Modeling of Discharging Currents Through IC Pins

Commercial integrated circuits (ICs) were assembled on several practical printed circuit board (PCB) structures, and the discharging currents through individual pins of the IC induced by charged board events (CBE) were measured using shielded Rogowski coils. The overall CBE measurement setup was modeled and validated using circuit simulations. The structures of PCBs and a test ground plane were effectively modeled using a multilayered finite-difference method. Electrostatic discharge protection circuits in the IC were also modeled as behavioral circuit models. From the measurement and modeling of the CBE discharging currents at the IC pins, IC failure mechanisms were analyzed according to PCB structure, decoupling capacitor, and discharging points. Several strategies for IC protection against CBE risks were also obtained.