Byung Cheol Song

Multi-resolution block matching algorithm and its VLSI architecture for fast motion estimation in an MPEG-2 video encoder

This paper proposes a high-performance multi-resolution motion estimation algorithm (HMRME) for MPEG-2 video encoding, which satisfies high estimation performance and efficient very large scale integration (VLSI) implementation. HMRME is based on a characteristic that field motion vectors (MVs) are very similar to their corresponding frame MV. Firstly, HMRME performs frame-based motion estimation (ME) as follows: at the coarsest level, two MV candidates are found on the basis of minimum matching error. The two MV candidates from the coarsest level search and the other one based on spatial MV correlation are used as center points for three local searches at the middle level. At the finest level, a frame MV is obtained from a local search around a single candidate from the middle level search. Field MVs are estimated with the single MV candidate from the middle level search of frame ME as initial estimates at the finest level, without any coarser level searches. This paper also describes a VLSI architecture based on HMRME. This architecture is designed to provide a good tradeoff between on-chip memory size and I/O bandwidth with high throughput. We implemented this architecture with about 140 K gates and 2.5 K bytes static random access memory for a large search range of [-192.0, +191.5] by using a synthesizable Verilog HDL.

Noise power estimation for effective de-noising in a video encoder

This paper presents a noise estimation algorithm using multiresolution motion estimation in a video encoder. Firstly, the motion estimator finds minimum block-matching errors at the finest resolution and the middle resolution for each macroblock. Secondly, if the minimum block-matching error at the finest resolution of a certain macroblock is less than a particular threshold, the variance of the inter-macroblock is computed. And then, we employ the square of the minimum block-matching error at the middle resolution as a predictor of the variance of the desired inter-macroblock without noise. The noise variance in the macroblock can be estimated by subtracting the predictor from the variance of the inter-macroblock. Finally, the noise variances estimated only for the well-motion-compensated macroblocks are averaged in each frame. Experimental results show that the proposed noise estimation is very accurate with negligible computational cost.

A one-pass variable bit-rate video coding for storage media

The paper presents a one-pass VBR coding algorithm, which provides high visual quality and satisfies a target bit-budget constraint. Since the proposed algorithm exploits the remaining bit amount instead of average bit-rate in determining quantization scale, it can balance the target bit-budget. Simulation results show that the proposed algorithm is superior to the MPEG-2 TM5 constant bit-rate (CBR) control in term of PSNR. The proposed algorithm also achieves real-time VBR video encoding requiring high visual quality for storage media.

An intra-frame rate control algorithm for ultra low delay H.264/AVC coding

In this paper, we present an intra-fame rate control algorithm for ultra low delay H.264/AVC coding. In real time video coding, all the macro-blocks within a current frame may be unavailable before encoding them. Hence the proposed scheme predicts relative complexity of the current block from complexity of available macro-blocks within previous and current frames. Then, the algorithm allocates bits to each macro-block considering the relative complexity between the macro-block and the current frame. Quantization parameter of each macro-block is obtained by comparing the generated and allocated bits and is refined for improving coding performance. The required buffer size is only around one-third of average bits required for encoding a single frame. Simulation results show that the proposed algorithm can prevent the buffer from overflow and underflow while it provides better coding performance.

Motion-compensated temporal prefiltering for noise reduction in a video encoder

For coding efficiency as well as noise reduction, efficient prefiltering needs to be performed prior to video encoding. This paper presents a DCT-domain temporal filtering scheme in an MPEG video encoder. It is proven that the multiplication of every DCT coefficient in an inter block with a proper weight is equivalent to motion compensated temporal filtering in the spatial domain for the inter block. Also, we propose to determine properly the weight by using effective noise estimation scheme. Experimental results show that the proposed prefiltering scheme provides outstanding coding efficiency as well as noise reduction in an MPEG video encoder.

Transform-domain Wiener filtering for H.264/AVC video encoding and its implementation

For coding efficiency as well as noise reduction, efficient de-noising needs to be performed prior to video encoding. This paper proposes a transform-domain Wiener filtering scheme in an H.264/AVC video encoder. We show that the generalized Wiener filtering for each integer-transformed block is equivalent to multiplication of multiplication factor (MF) in a block with a proper filter coefficient matrix in a quantization process. Also, we implement efficiently the proposed scheme by employing several predetermined modified MFs for quantization. Experimental results show that the proposed de-noising scheme provides outstanding coding efficiency as well as noise reduction in an H.264/AVC video encoder.

A rate-constrained fast full-search algorithm based on block sum pyramid

This paper presents a fast full-search algorithm (FSA) for rate-constrained motion estimation. The proposed algorithm, which is based on the block sum pyramid frame structure, successively eliminates unnecessary search positions according to rate-constrained criterion. This algorithm provides the identical estimation performance to a conventional FSA having rate constraint, while achieving considerable reduction in computation.

Efficient video transcoding with scan format conversion

General-purpose MPEG-2 video transcoders must be able to achieve any conversion between 18 ATSC (Advanced Television System Committee) video formats for DTV (digital television), e.g., scan format, size format, and frame rate format conversion. Especially, scan format conversion is hard to implement because frame rate and size format conversion often happen together. This paper proposes a fast motion estimation (ME) algorithm for MPEG-2 video transcoding supporting scan format conversion. Firstly, we extract and compose a set of candidate motion vectors (MVs) from the input bit-stream to comply with the re-encoding format. Secondly, the best MV is chosen among several candidate MVs by using a weighted median selector. Simulation results show that the proposed ME algorithm reduces significantly transcoding complexity with a minor PSNR degradation.

A novel CAVLC architecture for H.264 Video encoding at high bit-rate

In H.264/AVC and the variants, the coding of context-based adaptive variable length codes (CAVLC) is one of the demanding operations, particularly for high bitrates such as 100 Mbps. This paper presents a novel architecture that exploits component-level parallelism and pipeline techniques capable of processing high-bitrate video data in a macroblock(MB)-level pipelined CODEC architecture. Additionally, some techniques for efficient CAVLC coding is presented because CAVLC is a dominant part of the syntax coding. The resulting architecture, merged in a MB-level pipelined CODEC system, is capable of coding up to 100 Mbps bitstreams in real-time, thus, accommodating the real-time encoding of 1080p 60 Hz video.

Fast multi-resolution motion estimation algorithm and its VLSI architecture

This work presents a fast multi-resolution block-matching algorithm (FMRME) for MPEG-2 video encoding, which provides an outstanding PSNR performance close to the full search algorithm. We also propose the hardware architecture of the FMRME for real-time MPEG-2 video encoding with a large search range of [-192.0, +191.5]. Due to efficient data reuse and parallel processing, the utilization percentage of PE is also very high. We implemented this architecture with about 100 K gates and 5 K bytes SPSRAM.