Byung-Hyuk Min

A novel offset gated polysilicon thin film transistor without an additional offset mask

We have proposed a novel offset gated polysilicon TFT fabricated without an offset mask in order to reduce leakage current and suppress the kink effect. The photolithographic process steps of the new TFT device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The novel TFT also exhibits a considerable reduction in the kink effect because a very thin film TFT may be easily fabricated due to the elimination of the contact over-etch problem. >

Structural Dimension Effects of Plasma Hydrogenation on Low-Temperature Poly-Si Thin Film Transistors

The effects of plasma hydrogenation on various N- and P-channel polycrystalline-silicon (poly-Si) thin film transistors (TFTs) fabricated at a maximum temperature of 600° C were analyzed systematically. Device characteristics, such as threshold voltage and field-effect mobility, were improved significantly with hydrogenation time as the channel length of poly-Si TFTs was decreased from 20 µm and 2.5 µm. However, hydrogenation effects on the characteristics of poly-Si TFTs, of which channel width was varied from 2.5 µm to 20 µm, were almost identical. In thin active layer (50 nm) TFTs, the device performance was improved significantly compared with thick (100 nm and 150 nm) devices with hydrogenation time while the thickness of gate poly-Si may not be directly related with hydrogenation effects, probably due to the fact that the hydrogen atoms may diffuse along the channel region while the diffusion of hydrogen atoms through gate poly-Si may be negligible.

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained.We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained.

A novel lateral field emitter triode with insitu vacuum encapsulation

We have designed and fabricated a novel lateral field emitter triode, which is in-situ vacuum encapsulated so that any troublesome additional vacuum sealing process is not required. The device exhibits low turn-on voltage of 7 V, stable current density of 2 /spl mu/A/tip at V/sub AC/=30 V, and high transconductance of 1.7 /spl mu/S at V/sub AC/=22 V. An in-situ vacuum encapsulation employing recessed cavities by isotropic RIE (Reactive Ion Etch) method and an electron beam evaporated molybdenum vacuum seals is implemented to fabricate a new field emitter triode.

A novel polysilicon thin-film transistor with a p-n-p structured gate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFTs process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably.

Novel offset gated poly-Si TFTs with subgate

We have fabricated a new offset gated poly-Si TFT by employing photoresist reflow, have measured various experimental data of the new device, such as hydrogenation results and high-frequency characteristics, and have analyzed device characteristics as a function of driving frequency. Our devices have a unique gate pattern and the hydrogenation effect is somewhat different from the previous results. Our experimental results suggest that with the same offset length, the device with a wider space between the maingate and the subgate is more advantageous for hydrogenation. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device in the typically used frequency range (10-100 kHz).

Electrical characteristics of poly-Si TFT's with smooth surface roughness at oxide/poly-Si interface

We have fabricated a polycrystalline silicon thin film transistor (poly Si TFT) using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. Compared with the poly-Si TFTs fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength, and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to he critical to enhance the device performance.

Performance of Poly-Si Tfts with Double Gate Oxide Layers

We have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.

Pulsed-laser-induced crystallization of fluorinated amorphous and microcrystalline silicon films

Laser annealing effects in fluorinated amorphous and microcrystalline silicon, in which the crystalline fraction is varied, have been investigated. The initial film structure, as characterized by the crystalline fraction, is found to influence the laser-induced grain growth behavior. The surface melting time and solidification time, which are related to the grain growth, are increased in the film with a critical initial crystalline fraction, promoting grain growth and grain quality.

A new poly-Si TFT to improve surface roughness at poly-oxide/poly-Si interface

We have fabricated a poly-Si TFT using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. The surface roughness at the interface is observed by transmission electron microscopy (TEM) and is also evaluated by atomic force microscopy (AFM) after the oxide layer is removed using buffered HF acid. Compared with the poly-Si TFTs fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to be critical to enhance the device performance.