Byung In Moon

An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine

There are several shortest-path search algorithms such as A-star, D-star and Dijkstra. These algorithms are widely used in automotive vehicles and mobile navigation systems. As the number of nodes is increased considerably, the shortest-path algorithms implemented in software produce heavily computational overhead. In this paper, in order to avoid computational overhead, we propose a hardware model of the A-star algorithm for the shortest-path search engine. Especially, we propose shift register based on efficient hardware model and show simulation results in comparison with previous works.

System-Level Development and Verification of the FlexRay Communication Controller Model Based on SystemC

The FlexRay network protocol will replace the role which the CAN protocol has for in-vehicle backbone networks. A FlexRay communication controller model based on SystemC, combined with other SystemC models and RTL IPs, can be simulated in a system level through various simulation tools. This paper proposes the method of developing the model of a FlexRay communication controller based on SystemC and the techniques for verifying it. We have analyzed FlexRay SDL descriptions which represent the core mechanisms of the communication controller. From this analysis, this paper develops a FlexRay communication controller model based on SystemC. Several tools and additional models for simulation are used to build up the simulation environment for system-level verification. Our simulation environment can be configured to verify the FlexRay communication controller model in various communication environments.

An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search

In this paper, a modified ant colony system (ACS) algorithm is proposed to find a shortest path based on the preference of links. Most of the shortest path search algorithms aim at finding the distance or time shortest paths. However, these shortest paths are not surely an optimum path for the drivers who prefer choosing a less short, but more reliable or flexible path. For this reason, we propose the preference-based shortest path search algorithm which uses the properties of the links of the map. The properties of the links are specified by a set of data provided by the user of the car navigation system. The proposed algorithm was implemented in C and experiments were performed upon the map that includes 64 nodes with 118 links.

A Digit Reversal Circuit for the Variable-Length Radix-4 FFT

When the fast Fourier transform (FFT) is executed using an in-place method, the input or output data must be accessed in a digit-reversed order. The previous digit reversal circuits, which are based on a binary counter, require complex multiplexers. This paper proposes a new digit reversal circuit based on two-bit counter modules for the variable-length radix-4 FFT. This circuit can be designed with minimal multiplexers, and thus can efficiently generate digit-reversed sequences compared with digit reversal circuits based on a binary counter.

High-Speed Priority Queue Architecture for Multiple Out Links

As internet use widely, the concept of QoS(quality of service) is more emphasized. In this paper, we proposed high speed priority queue for guaranteeing QoS. Differ from previous priority queue, this architecture can input or output numerous data at once using special control block. So, this architecture is more suitable for recent fast networks. Moreover it can reduce area support for multiple out links in one.

A Low-Cost Recovery Mechanism for Processors with Large Instruction Windows

The latest processors employ a large instruction window and longer pipelines to achieve higher performance. Although current branch predictors show high accuracy, the misprediction penalty is getting larger in proportion to the number of pipeline stages and pipeline width. This negative effect also happens in case of exceptions or interrupts. Therefore, it is important to recover processor state quickly and restart processing immediately. In this letter, we propose a low-cost recovery mechanism for processors with large instruction windows.

Improved reinforcement computing to implement antnet-based routing using general NPS for ubiquitous environments

In the ubiquitous convergence era, the traffic managements and quality of services will be made much of a role. Because traditional routing mechanisms are lacking scalability and adaptability, a kind of adaptive routing algorithm called AntNet has attracted the attention. AntNet is an adaptive agent-based routing algorithm that imitates the activities of the social insect. In AntNet, there are implementation constraints due to complex arithmetic calculations for determining a reinforcement value. Besides, a housekeeping core in network processors will be overwhelmed by increasing routing workload for a processing of agents. In this paper, we propose a new reinforcement computing algorithm to overcome these problems. This can be implemented efficiently on packet forwarding engines of conventional network processors. The simulation results show that the proposed AntNet is more adaptive and effective in the performance of the implementation than the original AntNet.

A practical test scheduling using network-based TAM in network on chip architecture

It may be impractical to have TAM for test usage only in NoC because it causes enormous hardware overhead. Therefore, the reuse of on-chip networks for TAM is very attractive and logical. In network-based TAM, an effective test scheduling for built-in cores is also important to minimize the total test time. In this paper, we propose a new efficient test scheduling algorithm for NoC based on the reuse of on-chip networks. Experimental results using some ITC’02 benchmark circuits show the proposed algorithm can reduce the test time by about 5 – 20% compared to previous methods. Consequently, the proposed algorithm can be widely used due to its feasibility and practicality.