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Dive into the research topics where C. Bharatiraja is active.

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Featured researches published by C. Bharatiraja.


ieee region international conference on computational technologies in electrical and electronics engineering | 2008

Comparative realization of different SVPWM schemes in linear modulation using FPGA

C. Bharatiraja; T. Balaji Prasad; R. Latha

This paper presents implementation of different space vector pulse width modulation (SVPWM) switching patterns in linear modulation for three phase voltage source inverters (VSI) using FPGA and comparative analysis of them. The sequence most favored in the literature is not the best one for all applications. Such is the diversity of digital motor control that it is sometimes difficult to determine which technique is best suited for a particular application. The main objective of this paper is to analyze different schemes that are best suitable for different applications. The integration of VLSI core with a set of useful peripherals significantly simplifies the implementation of SVPWM technique for three phase inverters. Both simulation and experimental results are presented.


IEEE Journal of Emerging and Selected Topics in Power Electronics | 2018

A Timing Correction Algorithm-Based Extended SVM for Three-Level Neutral-Point-Clamped MLI in Over Modulation Zone

C. Bharatiraja; S. Jeevananthan; Josiah L. Munda

The space vector modulation readied multilevel inverter (MLI) has become palpable in industrial drives. The operation of voltage-source inverter drives in the overmodulation (OVM) mode is necessary as it patronages the extended speed range of the ac drives. This paper proposes a timing correction algorithm (TCA) to incorporate the OVM mode in space vector pulsewidth modulation (SVPWM) for the three-phase three-level neutral-point-clamped (NPC) MLI drive. First, the boundary restriction inherited in the hexagonal space vector diagram of linear modulation (LM) is redefined/quantified as modulation depth loss factor and computed for various values of modulation index belongs to the OVM region. Next, the appropriate time correction is carried out in the switching vector timings. The TCA insinuatingly corrects these magnitude gains and losses in terms of addition and subtraction of the corrective term in the on-time of the switches. The proposed timing corrected SVPWM strategy hosts a simple assessment and a duty-cycle recalculation procedure for determining on-times. This avoids the conventional nonlinear function and the lookup table. The proposed TCA-based SVPWM is simulated in LM and OVM regions using MATLAB/Simulink, and the corroboration is done using a field programmable gate array SPARTAN-III-3AN-XC3S400 architecture on 2-kW three-phase three-level NPC-MLI fed ac drive.


ieee international conference on renewable energy research and applications | 2016

A common-mode leakage current mitigation for PV-grid connected three-phase three-level transformerless T-type-NPC-MLI

C. Bharatiraja; J.L. Munda; Ramazan Bayindir; Mohd Tariq

Neutral point Multilevel inverter (NP-MLI) built Transformerless (TL) inverter topologies and its PWM techniques research in photovoltaic (PV) generation based grid connected system is more and more engrossed for the benefit of high efficiency, reliability, and low cost. However, a common-mode (CM) leakage current is very serious issue in these inverters, which is main causes of the gird interface concern and exaggerates EMI problems. Hence, the CM leakage current must to be handled by avoiding CM voltage through inverter PWM. This paper is proposed a space vector modulation (SVM technique to mitigate the CM leakage current by selecting only mediums, and zero vector. The paper also investigated the CM leakage currents envisage and behavior for the there-phase MLI through inverter switching function, which is not discussed before. The effectiveness of the proposed PV tied gird connected TL-TNP-MLI has been verified through the MATLAB/Simulink simulation model and FPGA based experiment results for a 1.5-kW system.


Archive | 2018

Modelling and Analytical Study of Linear Induction Motor and Its Air Gap Flux Measurement at Different Slip

Prasenjit D. Wakode; Mohd Tariq; T. K. Bhattacharya; C. Bharatiraja

The paper presents a complete modelling and analysis of the Linear Induction Motor (LIM). The dimensions of the different parts of LIM prototype are given in the paper. The main air gap flux component, i.e. Y components (magnetic flux density distribution B y (x, t) is calculated using the theoretical equations and compared with the MATLAB®/Simulink-based results. The analysis of the primary winding is also presented in the paper and it is traced from the flux density when only phase “A” is energized.


ieee international conference on power electronics intelligent control and energy systems | 2016

Performance analysis and modeling of high efficiency medium power Resonant Dual Active Bridge converter for wireless power transfer

Mohammad Tauquir Iqbal; Mohd Tariq; Ali I. Maswood; Pratik Biswas; C. Bharatiraja; Vimlesh Verma

Demand for the contactless power transfer or wireless power transfer is increasing. Wireless power can be achieved across large air gap which will be backbone for the future automation industry. This paper presents the analysis, design and simulation studies of the CLC based Resonant Dual Active Bridge (RDAB) topology for the inductive wireless power transfer application in the hybrid electric vehicle. The main advantage of RDAB topology to the Conventional Dual Active Bridge (DAB) topology is the requirement of less reactive power due to the “Resonance” created by CL (capacitor + inductor) circuit in the primary and a Capacitor in the secondary side of the high frequency transformer. The bridge current (switch current) is reduced due to the low reactive power and it helps in achieving high efficiency due to reduction in the conduction loss as well as power factor of the model. Reactive power is supplied by the capacitor in the primary side of the transformer. RDAB also provides Zero Voltage Switching at wide range of load. The complete system is analyzed and simulated in PSIM 9.1. The details analysis, simulation studies and comparison of the RDAB topology with the conventional dual active bridge topology is presented in the paper.


ieee international conference on power electronics drives and energy systems | 2016

Design and implementation of fourth arm for elimination of bearing current in NPC-MLI fed Induction motor drive

C. Bharatiraja; J.L. Munda; S. Raghu; Thanga Raj Chelliah; Mohd Tariq

The exploration result on increase in variable drive which creates an impact to prevail on the electric machine failure due to existence of bearing current. The bearing current associated with drive system is concerned about the operating frequencies of the solid state semiconductor switches which may cause the electrostatic charge between stator and rotor which eventually causes damage to windings and bearings. The various techniques comprised in literature to suppress the bearing currents like filter design, switching redundancy, common mode circuitry, isolated grounding scheme and grounding the motor shaft. This paper presents an innovative solution to suppress the bearing current by addition of a fourth arm circuitry to the neutral point of machine to obtain a zero at neutral potential. All the proposed circuitry and algorithm are simulated using MATLAB/Simulink and validation is done through a 2.2kW NPC-MLI laboratory prototype using a Xilinx family SPARTAN-III-3A XC3SD1800A-FG676 DSP-FPGA processor board


ieee international conference on power electronics drives and energy systems | 2016

Design of a proportional resonant controller for packed U cell 5 level inverter for grid-connected applications

Mohd Tariq; Mohammad Tauquir Iqbal; Mohammad Meraj; Atif Iqbal; Ali I. Maswood; C. Bharatiraja

In this paper, the design of a proportional resonant (PR) controller for the packed U cell (PUC) 5 level inverter is presented. The objective of the presented work is to present a better solution for current control in grid connected application of the investigated topology. A suitable LCL filter is designed along with the PR control scheme for grid connection. Simulation is performed in MATLAB®/Simulink simulation environment and the theoretical as well as simulation results are validated through experimental results. The simulation results shown in the paper includes both the steady state and the dynamic conditions. The key equations, block diagram, simulation results and experimental results are shown and discussed in the paper.


2014 Texas Instruments India Educators' Conference (TIIEC) | 2014

A Solar Power System for Electric Vehicles with Maximum Power Point Tracking for Novel Energy Sharing

Sushuruth Sadagopan; Sudeep Banerji; Priyanka Vedula; Mohammad Shabin; C. Bharatiraja

This paper presents a new system architecture which makes efficient use of the power produced from the photovoltaic (PV) panels used for charging batteries of solar powered electric vehicles. It has power systems for solar powered electric vehicles and solar powered grid which is connected to a charging station or a hub. Several electric vehicles may be charged with its own photovoltaic panel and the hub, which in turn is charged by a large capacity photovoltaic panel or by the electric grid in case the power provided by the panel is not sufficient. Once all the batteries connected to the system reach a certain maximum charge limit, excess energy from the vehicles and the hub is pumped into the grid, thus utilizing the energy that would have otherwise been wasted.


Applied Mechanics and Materials | 2013

FPGA Implementation of Three Dimensional SVPWM

S. Rajagopal; Sheba Charles; Priyanka Vedula; C. Bharatiraja; Subhranshu Sekhar Dash

In this paper includes an approach to implement Three Dimensional Space Vector Pulse width Modulation (3D-SVPWM) for multilevel inverter/Converter. The Proposed 3D-SVM scheme finds the reference vector by using simple mathematical equations for selecting switching states without redundant switching vectors. Moreover, the proposed PWM strategy satisfies the constraint that the output voltage vector should be only changed by one switching action. Not requiring extra hardware, the NPC inverter with the proposed PWM results are remarkable. The proposed algorithm is simulated by MATLAB and Implemented by FPGA-DSP Processor.


International Journal of Computer Applications | 2010

A System on Chip (Soc) - High-performance Power Drive Applications - SVPWM Based Voltage Source Inverter

C. Bharatiraja; Dr.S. Jeevanandam; Pratik

This paper presents a new circuit realization on single on chip for the space-vector pulse-width modulation (SVPWM) strategy. An SVPWM control integrated circuit (IC) has been developed using the state-of-the-art field-programmable gate array (FPGA) technology. The proposed SVPWM control scheme can be realized using only a single FPGA (XC4010) from Xilinx, Inc. presents the design and Implementation of library modules called Intellectual Property (IP) Cores to develop highperformance power drives and motion control applications. The Library is coded in VHDL for modularity and portability. Very frequently Power Drives and motion control applications are implemented using DSP or Microcontroller and algorithms are written in assembly or in a high level language such as ‗C.‘ By using VHDL to describe the circuit we implement algorithms directly in hardware instead of writing sequential programs. The realization includes the module of the implementation of Space Vector Pulse Width Modulation (SVPWM) switching patterns for three phases Voltage Source Inverters (VSI) which plays a vital role in the induction machine control. The objectives is to present a survey on the advancement recently introduced in the design of electronic circuits and to discuss how they can be implemented in Industrial Electronics industry to pace with the new wave of global competition. In this work a methodology for developing the IP cores for Power Drive and Motion Control Applications is proposed. The advantages of this implementation are to reduce the cost by embedding them in a single chip, to achieve the processing speed incomparable to that of sequential flow program of DSP‘s and Microprocessors, to make them application specific and they can be enhanced to suit future complex requirements.

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S. Jeevananthan

Pondicherry Engineering College

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Josiah L. Munda

Tshwane University of Technology

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Mohd Tariq

Nanyang Technological University

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Thanga Raj Chelliah

Indian Institute of Technology Roorkee

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