C. El Salloum

The time-triggered System-on-a-Chip architecture

It is the objective of the presented System-on-a-Chip (SoC) architecture to provide a predictable integrated execution environment for the component-based design of many different types of embedded applications (e.g., automotive, avionics, consumer electronics). At the core of this architecture is a time-triggered network-on-a-chip for the predictable interconnection of heterogeneous components. A component can be a self-contained computer, including system and application software, an FPGA, or a custom hardware unit. By providing a single uniform interface to all types of components for the exchange of messages, the architecture supports the component-based design of large applications and enables the massive reuse of components. The time-triggered network-on-a-chip offers inherent fault isolation to facilitate the seamless integration of independently developed components, possibly with different criticality levels. Furthermore, mechanisms for integrated resource management support dynamically changing resource requirements (e.g., different operational modes of an application), fault-tolerance, a power-aware system behavior, and the implementation of fault-handling by reconfiguration.

From a Federated to an Integrated Automotive Architecture

This paper describes an integrated system architecture for automotive electronic systems based on multicore systems-on-chips (SoCs). We integrate functions from different suppliers into a few powerful electronic control units using a dedicated core for each function. This work is fueled by technological opportunities resulting from recent advances in the semiconductor industry and the challenges of providing dependable automotive electronic systems at competitive costs. The presented architecture introduces infrastructure IP cores to overcome key challenges in moving to automotive multicore SoCs: a time-triggered network-on-a-chip with fault isolation for the interconnection of functional IP cores, a diagnostic IP core for error detection and state recovery, a gateway IP core for interfacing legacy systems, and an IP core for reconfiguration. This paper also outlines the migration from todays federated architectures to the proposed integrated architecture using an exemplary automotive E/E system.

A resource management framework for mixed-criticality embedded systems

Dynamic resource management enables a system to dynamically react to changing resource demands or resource availability. It enables better resource utilization, improved dependability, and the enabling of power-aware system behavior. This paper examines the application of dynamic resource management for an integrated time-triggered system architecture for embedded systems, which is designed to support mixed-criticality systems, i.e., systems integrating distributed application subsystems (DASs) with different dependability requirements on the same hardware platform. For such systems a vital characteristic is to achieve encapsulation of the hosted DASs and to provide mechanisms for fault-isolation. The key challenge addressed in this paper is to preserve these system characteristics despite the presence of dynamic resource allocation. To this end, a resource management framework is presented that provides static resource guarantees for DASs having higher dependability requirements, while facilitating efficient resource utilization for less critical DASs.

DECOS: an integrated time-triggered architecture

Depending on the physical structuring of large distributed safety-critical real-time systems, one can distinguish federated and integrated system architectures. This paper describes an integrated system architecture which combines the complexity management advantages of federated systems with the functional integration and hardware benefits of an integrated approach. In order to control complexity, the overall functionality is divided into a set of application subsystems, each with dedicated architectural communication services, allowing developers to act as if they were building an application for a federated architecture. The introduced architecture builds upon the validated services of a time-triggered core architecture, which provides a physical network as a shared resource for the communication activities of more than one application subsystem. The communication resources are encapsulated and multiplexed between application subsystems. In analogy, encapsulated partitions are used to share node computers among software modules of multiple application subsystems. Architectural encapsulation mechanisms ensure that the assumptions and abstractions performed in the functional system structuring also hold after combining the different subsystems on the target platform.In Abhängigkeit der physikalischen Strukturierung von großen verteilten sicherheitskritischen Echtzeitsystemen können föderierte und integrierte Systemarchitekturen unterschieden werden. Diese Arbeit beschreibt eine integrierte Systemarchitektur, welche die Vorteile föderierter Architekturen in Bezug auf Komplexitätsmanagement mit den Vorteilen eines integrierten Ansatzes (d. h. bessere funktionale Integration und Ressourcenauslastung) vereint. Um die Komplexität des Gesamtsystems zu beherrschen, erfolgt eine Unterteilung in Applikationssubsysteme, die zudem mit spezifischen Architekturdiensten ausgestattet sind. Insbesondere werden die Kommunikationsdienste in deren Funktionalität und Zeitverhalten an die jeweiligen Applikationsanforderungen angepasst. Designer können das System daher in einer Weise entwickeln, wie dies eine föderierte Architektur gestatten würde. Die vorgestellte integrierte Systemarchitektur basiert auf den validierten Diensten einer zeitgesteuerten Kernarchitektur, wobei das physikalische Netzwerk eines einzelnen, verteilten zeitgesteuerten Computersystems als gemeinsame Ressource für die Kommunikationsaktivitäten mehrerer Applikationssubsysteme dient. Die Kommunikationsressourcen werden enkapsuliert und zwischen Applikationssubsystemen gemultiplext. Ebenso dienen enkapsulierte Partitionen innerhalb von Komponenten der Aufteilung von Komponentenressourcen (z. B. Prozessorzeit und Speicher) zwischen Softwaremodulen verschiedener Applikationssubsysteme. Die Enkapsulierungsmechanismen der Architektur auf Netzwerk- und Komponentenebene stellen sicher, dass die im Rahmen der funktionalen Systemstrukturierung getroffenen Annahmen und Abstraktionen auch nach der Integration der verschiedenen Subsysteme auf der Zielplattform halten.

Composability in the time-triggered system-on-chip architecture

The composition of a large SoC out of pre-validated IP-cores requires an architecture that enables the seamless integration of components, i.e. composability. In this paper we present the five principles of composability that must be supported by any architecture that claims to enable the constructive composition of components. After the introduction of the TTSoC architecture and a description of a prototype implementation we show how this architecture conforms to the principles of composability.

Error Containment in the Time-Triggered System-On-a-Chip Architecture

It is the objective of the presented System-on-a-Chip (SoC) architecture to provide a predictable integrated execution environment for the component-based design of many different types of embedded applications (e.g., automotive, avionics, consumer electronics). At the core of this architecture is a time-triggered network-on-a-chip for the predictable interconnection of heterogeneous components. A component can be a self-contained computer, including system and application software, an FPGA, or a custom hardware unit. By providing a single uniform interface to all types of components for the exchange of messages, the architecture supports the component-based design of large applications and enables the massive reuse of components. The time-triggered network-on-a-chip offers inherent fault isolation to facilitate the seamless integration of independently developed components, possibly with different criticality levels. Furthermore, mechanisms for integrated resource management support dynamically changing resource requirements (e.g., different operational modes of an application), fault-tolerance, a power-aware system behavior, and the implementation of fault-handling by reconfiguration.

Fault isolation with intermediate checks of end-to-end checksums in the Time-Triggered System-on-Chip Architecture

This paper deploys end-to-end message checksums for error detection in the Time-Triggered System-on-Chip Architecture (TTSoCA). The end-to-end checksums are not only checked at the end, but also intermediately in the communication subsystem of the System-on-Chips (SoCs) concurrently with the message transmission in order to isolate faults: if a message transmission error occurs, the goal is to pinpoint whether the fault has originated in an IP core, in the communication subsystem, or in a gateway.

Integrating safety and multimedia subsystems on a Time-Triggered System-on-a-Chip

The time-triggered system-on-a-chip (TTSoC) architecture enables the realization of mixed-criticality systems using SoCs. The integration of subsystems with different criticality enables massive cost reduction by reducing the overall number of devices and networks (e.g., ECUs in car). To accomplish this goal, the TTSoC architecture offers inherent fault isolation mechanisms that prevent any unintended interference between application subsystems of different criticality. This paper demonstrates these capabilities using an exemplary automotive example with a safety-critical control subsystem and a multimedia subsystem. In the demo application, it is ensured by-construction that any design fault in the multimedia subsystem cannot have any adverse effect on the safety-critical control subsystem.

A Novel Naming Scheme for System-on-a-Chips Supporting Dynamic Resource Management

The problem of naming has been extensively studied in the field of distributed systems. However, multi-processor system-on-a-chips (MPSoCs), which are becoming more and more important in the construction of complex embedded systems, exhibit unique challenges with respect to naming. These challenges are induced by the need for dynamic resource management, independent development of IP cores and application subsystems, complexity management during system integration, and support for heterogeneous application domains. The solution proposed for naming in this paper is part of the time-triggered system-on-a-chip (TTSoC) architecture, which is a novel system architecture for MPSoCs. In particular, the developed naming scheme supports the integration of large embedded systems comprising multiple application subsystems (e.g., multimedia, comfort, powertrain in a car), each with its own dedicated domain-specific namespace. Furthermore, the TTSoC architecture provides gateways to support the construction of clusters of multiple SoCs, which creates the need for a naming scheme that establishes a uniform namespace across systems of systems.