C.R. de Boer

Low-loss phased-array based 4-channel wavelength demultiplexer integrated with photodetectors

A 4-channel phased-array wavelength division demultiplexer with 1.8 nm channel spacing at 1.54 /spl mu/m has been monolithically integrated with photodetectors in InP/InGaAsP. On chip losses are 3.5 to 4.5 dB. These are the lowest losses reported so far for demultiplexers monolithically integrated with photodetectors. Nearest neighbor crosstalk ranges from /spl minus/12 to /spl minus/21 dB.<<ETX>>

High aspect ratio through-wafer interconnections for 3D-microsystems

Closely spaced, through-wafer interconnects are of large interest in RF MEMS and MEMS packaging. In this paper, a suitable technique to realize large arrays of small size through-wafer holes is presented. This approach is based on macroporous silicon formation in combination with wafer thinning. Very high aspect ratio (/spl ges/ 100) structures are realized. The wafers containing the large arrays of 2-3/spl mu/m wide holes are thinned down to 200-150/spl mu/m by lapping and polishing. Copper electroplating is finally employed to realize arrays of high aspect ratio Cu plugs.

MEMS hotplates with TiN as a heater material

Titanium nitride has been investigated as a heater material for hotplates and microreactors. TiN is CMOS compatible, and has a higher melting point (2950 degC) than conventional heaters of Pt and poly-Si. For the first time, TiN is tested inside a conventional membrane of LPCVD SiNx. Two types of TiN are considered: high stress and low stress. Their performance is compared with that of Pt. The maximum temperature of TiN coils is 11% higher than Pt coils with the same layout and over 700 degC. For high-stress TiN, the TCR is almost constant and close to that of Pt, making it very suitable for temperature sensing. In the case of low-stress TiN the TCR becomes nonlinear and changes sign. The large differences between the nitrides are explained by the grain structure. Low-stress TiN contains many voids. They relax stress but strongly scatter the conduction electrons. The different grain structures are related to the sputtering parameters according to the Thornton model

Planar antiresonant reflecting optical waveguides as sensors for liquid substances

In this paper, we present the use of planar antiresonant reflecting optical waveguide (ARROW) as sensor for liquid substances. With a suitable design, a strong variation of the waveguide attenuation can be obtained by simply varying the refractive index of the cover cladding. In this configuration the waveguide acts like a vertical interferometer and can be used as an integrated refractometer. Fabrication of the device is accomplished using a silicon substrate and a process technology (PECVD) that is fully compatible with bipolar and CMOS IC processes. Preliminary measurements, performed using a flow cell clamped onto the surface of the sensor and filled with the analyte, show the validity of the approach.

Polyimide sacrificial layer for an all-dry post-process surface micromachining module

In this paper we present a novel post-process surface micromachining module that uses a commercial PI2610 polyimide as a sacrificial layer and PECVD SiC or SiN as structural layers. No wet etching is required thus avoiding stiction problems often encountered in wet sacrificial etching processes. A mask set containing cantilever beams, membranes, rotating structures, microswitches, etc. is applied to evaluate the potential of this process module. Silicon carbide micro-mechanical switches with different beam size are also designed and prepared using the three-mask process module suitable for appending to a CMOS fabrication sequence. A displacement /spl ges/15 /spl mu/m is achieved for 95 V and 235 V for the 1 /spl mu/m and 2 /spl mu/m wide silicon carbide beam, respectively.

Silicon nitride as dielectric in the low temperature SiGe HBT processing

Abstract Low-stress silicon-rich SiNx deposited at or below 700 °C by either LPCVD or PECVD has been studied for potential use in the surface processing of a 45 GHz SiGe HBT IC-process. The films underwent a thermal anneal at 700 °C and in all cases a thin oxide buffer layer was necessary for achieving suitable film quality.

The impact of route guidance, departure time advice and alternative routes on door-to-door travel time reliability: Two data-driven assessment methods

ABSTRACT Conventional travel time reliability assessment has evolved from road segments to the route level. However, a connection between origin and destination usually consists of multiple routes, thereby providing the option to choose. Having alternatives can compensate for the deterioration of a single route; therefore, this study assesses the reliability and quality of the aggregate of the route set of an origin-destination (OD) pair. This paper proposes two aggregation methods for analyzing the reliability of travel times on the OD level: 1) an adapted Logsum method and 2) a route choice model. The first method analyzes reliability from a network perspective and the second method is based on the reliability as perceived by a traveler choosing his route from the available alternatives. A case study using detailed data on actual travel times illustrates both methods and shows the impact of having variable departure times and the impact of information strategies on travel time reliability.

In-Situ Isotropic and Anisotropic DRIE Sequence for Massive Parallel Multistage Brownian Ratchets

In this paper an in-situ isotropic and anisotropic deep reactive ion etching (DRIE) sequence process is presented to obtain a periodic asymmetric variation along the z-axis in pore diameter on silicon wafers, which can act as massively parallel and multiply stacked Brownian ratchets. The etch rates of isotropic and anisotropic etching process depends strongly on the size and the shape of structures. The undercut phenomenon for small size structure (less than 2 mum) is investigated. Exposure into NH3 plasma after etching to smoothen the surface of silicon is discussed as well.

Transport mechanisms of a polysilicon emitter bipolar transistor with 8 nm gate oxide between emitter and base

The current mechanisms through 8 nm thermal oxide have been studied by integrating the MOS capacitor at the emitter-base junction in a bipolar NPN structure. The separation of the electron and hole flow into a collector and base current, respectively, enhances the possibility of identifying the origin of currents in MOS structures in general. Here, the temperature dependence of the generated charge carriers in relation to the tunneling current for both bias polarities on the gate has been measured. It is demonstrated that the anode hole injection concept can be excluded as the dominant current mechanism.

Non-catalyst and low temperature growth of vertically aligned carbon nanotubes for nanosensor arrays

In this paper we present a new technique to vertically grow aligned carbon nanotubes (CNTs) on nanosize pore anodic aluminum oxide (AAO) templates on a Si substrate. The CNTs are grown using methane in an RF PECVD system at only 400/spl deg/C without using a transition metal catalyst. The AAO templates are prepared by a two-step anodizing process in oxalic acid at room temperature. The influence of preparation conditions, such as temperature, electrolyte, applied voltage and anodization time on the density, diameter, length and the shape of the pores is investigated. The diameter of the pores of AAO film varies from 30 nm to 70 nm. The average diameter and length of CNTs are approximately 40 nm and 1 /spl mu/m respectively. This low temperature, IC-compatible process is very attractive as it allows integration of CNT devices with on-chip electronics.