C.T. Liu

Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs

The trend of CMOS technologies toward high-speed, low-power, and systems-on-a-chip has raised several urgent requirements on the gate dielectrics: (1) limited leakage current, (2) multiple thickness (t/sub ox/), (3) minimized variation or degradation of device threshold voltage (V/sub th/), transconductance (G/sub m/), and on-current (I/sub on/) at the finish of the device fabrication due to, e.g., oxide-nitridation-induced degradation or plasma-damage-induced degradation, (4) sustained device lifetime that has been difficult to achieve because of the aggressive device scaling, and (5) a practical and physical mean of qualifying thin gate dielectrics. The significance of each of the above requirements will be discussed, and recent efforts addressing these requirements will be reviewed.

Multiple gate oxide thickness for 2 GHz system-on-a-chip technologies

Multiple t/sub OX/ is thoroughly investigated for nitrogen-implanted gate oxides with the optimization of Q/sub BD/ and a demonstration of 2 GHz counters. Furnace growth at 800/spl deg/C, 850/spl deg/C, and 900/spl deg/C is compared with rapid-thermal-oxidation (RTO) at 1050/spl deg/C. A wide range of reduced growth rate, 20% to 80%, is achieved that meets the SIA road-map for the next few generations of the CMOS technology. Optimization of charge-to-breakdown (Q/sub BD/) is achieved through investigation of the nitrogen distribution profile in the oxide that is affected by the growth temperature, nitrogen implant dose, and post-oxidation anneals. 10/sup 15//cm/sup 2/ nitrogen dose results in a higher Q/sub BD/ as well as a tighter tail distribution of Q/sub BD/ than 5/spl times/10/sup 14//cm/sup 2/ nitrogen dose. The tight distribution of Q/sub BD/ is important for yield improvement. If the oxide is either grown or annealed at 900/spl deg/C, Q/sub BD/ is as good as the Q/sub BD/ of regular oxide without nitrogen. As an example of integration, 0.18-/spl mu/m CMOS devices with dual gate oxides of 3 nm and 4 nm are fabricated and characterized at 1.5, 1.8, and 2.5 V. Performance of divide-by-3 counters is evaluated with the consideration of parasitic RC delays, and the results are superior to the most recently published data. At room temperatures, the maximum toggle frequency (f/sub T/) is higher than 2 GHz for both 1.8 and 2.5 V operation, with a power dissipation of 3.4 /spl mu/W at 85/spl deg/C. To further reduce the power dissipation to 0.08 /spl mu/W, 1.5-V operation gives 1-GHz f/sub T/ also at 85/spl deg/C.

Light nitrogen implant for preparing thin-gate oxides

We have implanted nitrogen (N/sup +/) into Si substrates before growing thin thermal oxides, and discovered that light N/sup +/ doses of 5/spl times/10/sup 13/-5/spl times/10/sup 14//cm/sup 2/ reduced the oxidation rates by 20-30%. High-resolution TEMs and multiangle ellipsometry were used to study the oxides. The TEM reveals a highly uniform transition from the crystalline Si to the amorphous SiO/sub 2/. With a fixed index of refraction at 1.458 for the ellipsometry, the two measurements gave identical oxide thickness between 25 and 144 /spl Aring/, in contrast to the previously suggested 1.7 for oxides thinner than 100 /spl Aring/. In addition, the oxidation retardation was accompanied with an improvement of the oxide uniformity across the 6-in Si wafers. We also present results of n-channel MOSFETs with coded channel lengths varying from 0.2 /spl mu/m to 3 /spl mu/m. The implications of these findings in terms of VLSI technologies and oxidation chemistry are discussed.

Inverted thin-film transistors with a simple self-aligned lightly doped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L/sub ch/. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L/sub ch/, L/sub LDD/, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of approximately 1.25 mu A at 5 V and a leakage current of approximately 0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is approximately 7*10/sup 6/. >

Preventing boron penetration through 25-/spl Aring/ gate oxides with nitrogen implant in the Si substrates

For gate oxides thinner than 40 /spl Aring/, conventional schemes of incorporating N in the oxides might become insufficient in stopping B penetration. By implanting N into the Si substrates with a sacrificial oxide layer; we have grown 25 /spl Aring/ gate oxide and prevented B penetration in the presence of F after 90 min of 850/spl deg/C and 10 s of 1050/spl deg/C anneals. SIMS analyses surprisingly reveal a N peak formed within the thin oxide layer, while no N is left in the Si substrate beyond the oxide layer. In addition, no B is seen in the substrate, either. As a consequence, threshold voltage of pMOSFETs is shifted to a more negative value which agrees with calculations assuming no B penetration. Meanwhile, threshold voltage of nMOSFETs is not affected by the N implant, which confirms that B penetration is the only explanation for the pMOSFET data. Prevention of B penetration also improves the short-channel effects for 0.25-/spl mu/m pMOSFETs, while no difference is seen in nMOSFETs with and without N implant.

Intrinsic and stress-induced traps in the direct tunneling current of 2.3-3.8 nm oxides and unified characterization methodologies of sub-3 nm oxides

In devices with p+ gates and p- substrates, two unique conditions exist such that the intrinsic and stress-induced traps can be probed and separated in the direct tunneling current. The first condition is that E/sub F/ is initially below the midgap energy of the Si substrate. The second condition is that V/sub fb/ is near V/sub G/=0. Thus, E/sub F/ probes the trap states as it moves up toward E/sub C/. As a result, the increase in the tunneling current between V/sub fb/ and V/sub th/ (e.g., between V/sub G/=0.2 V and 1 V) is a very sensitive measurement of the intrinsic traps and can be used to qualify the initial quality of the oxides. Also under such conditions, the increase of the leakage current due to stress-induced traps can be clearly studied. Therefore, we propose that devices with p+ gates and p- substrates should be used to unify the characterization of ultrathin oxides. In fabricating dual-gate CMOS circuits, such devices can be made to qualify the oxides on product wafers. According to this study, several characteristics of the intrinsic and stress-induced traps can be concluded. Firstly, the intrinsic traps are fast states, and the stress-induced traps (after certain amount of stress) are mostly slow states. Secondly, the trap-assisted tunneling is an elastic process in the direct tunneling regime before stress. Finally, E/sub tr/, and Q/sub tr/, can be estimated from the direct tunneling current. The differences between intrinsic and stress-induced traps should be considered in developing breakdown models for ultrathin oxides.

Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress

In the fabrication of CMOS devices with sub-3 nm gate oxides, we have observed severe variation of the oxide thickness (t/sub ox/). For devices with 2.5 nm t/sub ox/ at the center of the channel, the physical t/sub ox/ ranges from 1.8 nm to 4.2 nm at various channel positions. This is caused by different oxide growth rates determined by the orientation and stress conditions of the local Si surface, especially at the rounded corners of the shallow-trench isolation (STI). In addition, poly-Si intrusion from the gate electrode also causes local t/sub ox/ thinning. Such severe variation of t/sub ox/ becomes the challenge of STI engineering, gate-oxide scaling and qualification.

High performance 0.2 /spl mu/m CMOS with 25 /spl Aring/ gate oxide grown on nitrogen implanted Si substrates

The difficulties in device engineering increase rapidly as advanced circuits take up more portions in the design of low-power IC products. These new circuit designs enforce strict requirements on the deep-submicron FETs, particularly in the areas of: (1) properties of thin gate oxides, (2) control of short channel effects, (3) doping profiles to reduce subthreshold slope and back-gate bias coefficient, and (4) device aging. Previously, we have shown that thin gate oxides grown on nitrogen implanted (N/sup +/ I/I) Si substrates can prevent boron (B) penetration for p-MOSFETs. Here, we have (1) built high performance 0.2 /spl mu/m CMOS with 25 /spl Aring/ gate oxide, (2) used multi-angle ellipsometry, high-resolution TEM, SIMS, XPS, and tunneling current to study the oxide properties, (3) identified N distribution in the oxide, (4) observed quantum effects in the oxide tunneling current, (5) compared hole and electron mobilities with and without N/sup +/ I/I, (6) demonstrated a range of V/sub th/, I/sub on/, and I/sub off/, (7) achieved 72 mV/dec subthreshold slope (SS), 60 mV Vth-shift under 2.5 V back-gate bias, and below 10 mV DIBL V/sub G/-shift, (8) studied junction leakage with and without N/sup +/ I/I, (9) oxide breakdown voltage, and (10) device lifetimes for both n- and p-MOSFETs.

Impact of nitrogen implant prior to the gate oxide growth on transient enhanced diffusion

The trend of reverse short channel effect (RSCE) with nitrogen implant dose, gate oxide thickness, and threshold implant dose have been measured and simulated. Thinner gate oxide reduces RSCE. Implanting nitrogen also reduces RSCE, but exactly in proportion to gate oxide reduction; no extra effect of the large nitrogen dose was found. Furthermore, a saturation of TED-induced dopant pile-up with accumulating implant dose is shown.

Plasma damage immunity of thin gate oxide grown on very lightly N/sup +/ implanted silicon

Plasma damage immunity of gate oxide grown on very low dose (2/spl times/10/sup 13//cm/sup 2/) N/sup +/ implanted silicon is found to be improved compared to a regular gate oxide of similar thickness. Both hole trapping and electron trapping are suppressed by the incorporation of nitrogen into the gate oxide. Hole trapping behavior was determined from the relationship between initial electron trapping slope (IETS) and threshold voltage shifts due to current stress. This method is believed to be far more reliable than the typical method of initial gate voltage lowering during current stress.