C. V. Ramamoorthy
University of Texas at Austin
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by C. V. Ramamoorthy.
IEEE Transactions on Computers | 1972
C. V. Ramamoorthy; K. M. Chandy; Mario J. Gonzalez
This paper describes a set of techniques that can be used to optimally schedule a sequence of interrelated computational tasks on a multiprocessor computer system. Using a directed graph model to represent a computational process, two basic problems are solved here. First, given a set of computational tasks and the relationships between them, the tasks are scheduled such that the total execution time is minimized, and the minimum number of processors required to realize this schedule is obtained. The second problem is of a more general nature. Given k processors, the tasks are scheduled such that execution time is again minimized. Consideration is given to tasks of equal and unequal duration, and task preemption is not allowed.
IEEE Transactions on Computers | 1972
K. M. Chandy; C. V. Ramamoorthy
Reliability is an important aspect of any system. On-line diagnosis, parity check coding, triple modular redundancy, and other methods have been used to improve the reliability of computing systems. In this paper another aspect of reliable computing systems is explored. The problem is that of recovering error-free information when an error is detected at some stage in the processing of a program. If an error or fault is detected while a program is being processed and if it cannot be corrected immediately, it may be necessary to run the entire program again. The time spent in rerunning the program may be substantial and in some real time applications critical. Recovery time can be reduced by saving states of the program (all the information stored in registers, primary and secondary storage, etc.) at intervals, as the processing continues. If an error is detected the program is restarted from its most recently saved state. However, a price is paid in saving a state in the form of time spent storing all the relevant information in secondary storage. Hence it is expensive to save the state of the program too often. Not saving any state of the program may cause an unacceptably large recovery time. The problem that we solve is the following. Determine the optimum points at which the state of the program should be stored to recover after any malfunction.
national computer conference | 1969
C. V. Ramamoorthy; Mario J. Gonzalez
State-of-the-art advances---in particular, anticipated advances generated by LSI---have given fresh impetus to research in the area of parallel processing. The motives for parallel processing include the following:n 1. Real-time urgency. Parallel processing can increase the speed of computation beyond the limit imposed by technological limitations.n 2. Reduction of turnaround time of high priority jobs.n 3. Reduction of memory and time requirements for housekeeping chores. The simultaneous but properly interlocked operations of reading inputs into memory and error checking and editing can reduce the need for large intermediate storages or costly transfers between members in a storage hierarchy.n 4. An increase in simultaneous service to many users. In the field of the computer utility, for example, periods of peak demand are difficult to predict. The availability of spare processors enables an installation to minimize the effects of these peak periods. In addition, in the event of a system failure, faster computational speeds permit service to be provided to more users before the failure occurs.n 5. Improved performance in a uniprocessor multi-programmed environment. Even in a uniprocessor environment, parallel processable segments of high priority jobs can be overlapped so that when one segment is waiting for I/O, the processor can be computing its companion segment. Thus an overall speed up in execution is achieved.
IEEE Transactions on Computers | 1972
C. V. Ramamoorthy; James R. Goodman; K. H. Kim
With the increasing availability of high-speed multiplication units in large computers it is attractive to develop an iterative procedure to compute division and square root, using multiplication as the primary operation. In this paper, we present three new methods of performing square rooting rapidly which utilize multiplication and no division. Each algorithm is considered for convergence rate, efficiency, and implementation. The most typical and efficient one of the already-known algorithms which utilizes multiplication, here called the N algorithm, is introduced for the purpose of comparison with the new algorithms. The effect and importance of the initial approximation is considered. (One of the algorithms, here called the G algorithm, is described in detail with the emphasis on its high efficiency.)
IEEE Transactions on Computers | 1971
Richard L. Kleir; C. V. Ramamoorthy
With increased use of microprogramming in present computer systems, the need arises to automate the checking and optimization of microcode. This paper reviews the optimization objectives, characterizes microprogranis, and discusses the machine structure. A translator from machine code to microcode appears feasible and is described. Some compiler techniques are reviewed and adapted to improve microprograms by studying operational interaction. Microprogram characteristics permit additional methods to reduce the computation effort. The techniques are integrated into a scheme implemented for optimizing a simulated machine.
IEEE Transactions on Computers | 1971
Mario J. Gonzalez; C. V. Ramamoorthy
This paper describes the Fortran parallel task recognizer and the directed graph model upon which it is based. The recognizer is itself a Fortran program. As input the recognizer accepts source programs written in Fortran; as output the recognizer generates a set of tables which communicate to the operating system information regarding the parallel processability of source program tasks. The recognizer has been used to analyze several programs in an attempt to determine what characteristics render a program suitable for parallel processing. Timing studies have shown that the detailed recognizer analysis consumes a large amount of time in an attempt to answer the suitability question. For a suitable production-type program this analysis time can be distributed over the lifetime of the program. In those cases where the source program is not suitable for parallel processing, however, this analysis represents a wasted investment of valuable system resources. To circumvent this, a heuristic procedure has been developed which introduces little overhead and provides a preliminary answer to the suitability question based solely on the nature and number of source program statements. If the preliminary analysis suggests a favorable potential for the source program, then the program is subjected to the detailed analysis of the recognizer.
IEEE Transactions on Computers | 1972
Mario J. Gonzalez; C. V. Ramamoorthy
The overhead involved in the real-time multiprocessor execution of parallel-processable segments of a sequential program is investigated. The execution follows a preprocessing phase in which the source program is analyzed and the parallel-processable segments are recognized. A number of representations of a parallel-processable program are possible. A table representation is used, and a technique is developed to efficiently interpret this table in a system in which a number of identical processors share a common memory.
IEEE Transactions on Computers | 1971
C. V. Ramamoorthy; Wataru Mayeda
In previous papers [3]–[5] the authors considered the application of graph theory to represent and analyze a computer system. From such analysis of the graph (thus the system), we have shown that faults can be detected and located by means of strategically placed test points within the system.
Communications of The ACM | 1971
C. V. Ramamoorthy; Mario J. Gonzalez
An arithmetic expression can often be broken down into its component subexpressions. Depending on the hardware environment in which the expression is to be executed, these subexpressions can be evaluated in serials, in parallel, or in a combination of these modes. This paper shows that expression execution time can be minimized only if consideration is given to the ordering of the subexpressions. In particular, subexpressions should be executed in order of decreasing memory and processor time requirements. This observation is valid for configurations ranging from a uniprocessor with an unbuffered main memory to a multiprocessor with a “cache” buffer memory. If the number of subexpressions which can be executed in parallel exceeds the number of available processors, then execution of some of these subexpressions must be postponed. A procedure is given which combines this requirement with the earlier ordering considerations to provide an optimal execution sequence.
IEEE Transactions on Computers | 1971
C. V. Ramamoorthy; Lih Chung Chang
In this paper we develop methods of segmenting a large system into smaller subsystems so that the letter can be diagnosed in parallel. Two basic techniques called serial segmentation and parallel segmentation are introduced. Furthermore, an algorithm is developed for the purpose of reducing the complexity and the size of the large subsystem.