C. Wissing

A fast high resolution track trigger for the H1 experiment

After 2001 the upgraded ep collider HERA will provide an about five times higher luminosity for the two experiments H1 and ZEUS. In order to cope with the expected higher event rates the H1 collaboration is building a track based trigger system, the Fast Track Trigger (FTT). It will be integrated in the first three levels (L1–L3) of the H1 trigger scheme to provide higher selectivity for events with charged particles. The FTT will allow to reconstruct 3-dimensional tracks in the central drift chamber down to 100 MeV/c within the L2 latency of ∼23 μs. To reach the necessary momentum resolution of ∼5% (at 1 GeV/c) sophisticated reconstruction algorithms have to be implemented using high density Field Programmable Gate Arrays (FPGA) and their embedded Content Addressable Memories (CAM). The final track parameter optimization will be done using non-iterative fits implemented in DSPs. While at the first trigger level rough track information will be provided, at L2 tracks with high resolution are available to form trigger decisions on topological and other track based criteria like multiplicities and momenta. At the third trigger level a farm of commercial processor boards will be used to compute physics quantities such as invariant masses. Keywords— Trigger, Fast Track Trigger, Track Trigger, FPGA, Content Addressable Memory, CAM, DSP, H1 Collaboration, HERA ColliderAfter 2001, the upgraded ep collider HERA will provide an about five times higher luminosity for the two experiments H1 and ZEUS. To cope with the expected higher event rates, the H1 collaboration is building a track-based trigger system, the Fast Track Trigger (FTT). It will be integrated in the first three levels (L1-L3) of the H1 trigger scheme to provide higher selectivity for events with charged particles. The FTT will allow reconstruction of three-dimensional tracks in the central drift chamber down to 100 MeV/c within the L2 latency of /spl sim/23 /spl mu/s. To reach the necessary momentum resolution of /spl sim/5% (at 1 GeV/c), sophisticated reconstruction algorithms have to be implemented using high-density field-programmable gate arrays and their embedded content addressable memories. The final track parameter optimization will be done using noniterative fits implemented in digital signal processors. While at the first trigger level rough track information will be provided, at L2 tracks with high resolution are available to form trigger decisions on topological and other track-based criteria like multiplicities and momenta. At the third trigger level, a farm of commercial processor boards will be used to compute physics quantities such as invariant masses.

A multifunctional processing board for the fast track trigger of the H1 experiment

The electron-proton collider HERA is being upgraded to provide higher luminosity from the end of the year 2001. In order to enhance the selectivity on exclusive processes a fast track trigger (FTT) with high momentum resolution is being built for the H1 collaboration. The FTT will perform a three-dimensional (3-D) reconstruction of curved tracks in a magnetic field of 1.1 Tesla down to 100 MeV in transverse momentum. It is able to reconstruct up to 48 tracks within 23 /spl mu/s in a high track multiplicity environment. The FIT consists of two hardware levels L1, L2 and a third software level. Analog signals of 450 wires are digitized at the first-level stage followed by a quick lookup of valid track segment patterns. For the main processing tasks at the second level such as linking, fitting, and deciding, a multifunctional processing board has been developed by the ETH Zu/spl uml/rich, Switzerland, in collaboration with Supercomputing Systems, Zu/spl uml/rich. It integrates a high-density field programmable gate array (FPGA) and four floating point digital signal processors (DSPs). This presentation will mainly concentrate on second trigger level hardware aspects and on the implementation of the algorithms used for linking and fitting. Emphasis is especially put on the integrated content addressable memory (CAM) functionality of the FPGA, which is ideally suited for implementing fast search tasks like track segment linking.

CMS computing operations during run 1

During the first run, CMS collected and processed more than 10B data events and simulated more than 15B events. Up to 100k processor cores were used simultaneously and 100PB of storage was managed. Each month petabytes of data were moved and hundreds of users accessed data samples. In this document we discuss the operational experience from this first run. We present the workflows and data flows that were executed, and we discuss the tools and services developed, and the operations and shift models used to sustain the system. Many techniques were followed from the original computing planning, but some were reactions to difficulties and opportunities. We also address the lessons learned from an operational perspective, and how this is shaping our thoughts for 2015.

First results from the first level of the H1 fast track trigger

The H1 experiment at the electron-proton collider HERA has built a new fast track trigger to increase the selectivity for exclusive final states and to cope with the higher background rates after the HERA luminosity upgrade. Hits measured in the central jet chamber of H1 are combined to track segments by performing 5times1012 mask comparisons per second using content addressable memories (CAMs). These segments are collected and transmitted via 5 Gbit/s LVDS links to custom made multi-purpose boards and linked to tracks. The latency of the fully pipelined processing chain implemented in programmable logic (FPGAs) is 0.72 mus. During the summer 2004 running period, the FTT level one system delivered first physics triggers from which performance figures were extracted. A single hit efficiency of more than 95% was achieved, and first studies on the pT resolution of tracks were performed using triggered rho meson candidates.