Can Zhu

A two-stage low-power amplifier with switch-capacitor common-mode feedback circuits

A low-power amplifier is designed to improve the performances of ADCs. The two-stage construction is adopted to provide bigger gain and wider swing at a power supply lower than 3.3V. Besides, the differential architecture is adopted to double the output swing while suppressing common noises. Special common-mode feedback circuits are designed to stable the common-mode outputs of the first and second stages but not to degenerate the output swing. A private switch is designed for the common-mode feedback circuits to eliminate the charge injection effect on the common-mode signals. The measurement results show that the ADC using the proposed amplifier has a SNR which is 4dB better than the ADC without the proposed amplifier.

High precision bandgap reference with chopping offset reducing technique

A CMOS bandgap reference using chopping technique for OPAMP offset cancelling is presented in this paper. The OPAMP used in bandgap was intended to improve the precision of the bandgap, but this aim is in some degree reduced by the input referred offset and 1/f noise of the introduced OPAMP. Thus, an effective architecture which contains three pairs of chopping cells is designed to overcome the issue above, while maintaining the stability of the closed feedback loop of the bandgap. The design is fabricated by a 0.18 µm 1P6M CMOS process. Measurements were performed between −55°C and +125°C, the results validated the techniques above, showing different performance of bandgap with/without chopping and with different chopping frequency. Comparing with the conventional design, the proposed architecture effectively improves the accuracy over temperature and process fluctuation.

A novel track and hold circuit with offset and gain calibration

A novel track and hold circuit in 0.18μm SiGe BiCMOS process is presented, whose offset and gain can be digitally calibrated, and which can be used in a time-interleaved ADC to improve its performances. The simulated results show that the proposed track and hold circuit can sample a signal at a rate of 1.25GHz, while consuming just 50mW. The offset calibration can get a range of 26.6mW with a step of 0.1mW, while the gain calibration gets a range of 33.28dB with a step of 0.13dB.

Dynamic latched comparator design for super-high speed analog-to-digital converter

As a building block of analog-to-digital converter (ADC), comparator plays an important role, especially the case latched comparator for super-high speed ADC. The speed and performance of latched comparator mostly decide the performance of the whole ADC. In this paper, a multi-stage purely dynamic high speed latched comparator for folding and interpolating ADC is designed with Bi-CMOS 0.18um process technology. The folding and interpolating ADC is employed in a four channel time interleaved ADC as a sub-ADC. The whole ADC can reach a sampling rate of 5GSPS at interleaved mode. As a result of measurement, the whole ADC can get a SNR of 45dB with the input frequency of 495MHz at the sample rate of 5GHz.

An 8-bit 5-Gsample/s Time-Interleaved Analog-to-Digital Converter Used for Optical Communication

In this paper, we present an 8-bit 5 Gsample/s time-interleaved analog-to-digital converter (TI ADC). A 4-phase low jitter clock is designed to control four 1.25 Gsample/s sub-ADCs which is implemented using folding and interpolating architecture. Digital calibration is used to adjust the offset error and gain error of sub-ADCs. Meanwhile, serial peripheral interface (SPI) is adopted to adjust mismatch of gain and sample time between sub-ADCs. The whole TI ADC is designed using a 0.18m SiGe BiCMOS process. The whole ADC has a SNR of about 45 dB at the input frequency of 495 MHZ and an equivalent ENOB of 7.2 bits.