Carmelo Vecchio

Nanoscale structural characterization of epitaxial graphene grown on off-axis 4H-SiC (0001)

In this work, we present a nanometer resolution structural characterization of epitaxial graphene (EG) layers grown on 4H-SiC (0001) 8° off-axis, by annealing in inert gas ambient (Ar) in a wide temperature range (Tgr from 1600 to 2000°C). For all the considered growth temperatures, few layers of graphene (FLG) conformally covering the 100 to 200-nm wide terraces of the SiC surface have been observed by high-resolution cross-sectional transmission electron microscopy (HR-XTEM). Tapping mode atomic force microscopy (t-AFM) showed the formation of wrinkles with approx. 1 to 2 nm height and 10 to 20 nm width in the FLG film, as a result of the release of the compressive strain, which builds up in FLG during the sample cooling due to the thermal expansion coefficients mismatch between graphene and SiC. While for EG grown on on-axis 4H-SiC an isotropic mesh-like network of wrinkles interconnected into nodes is commonly reported, in the present case of a vicinal SiC surface, wrinkles are preferentially oriented in the direction perpendicular to the step edges of the SiC terraces. For each Tgr, the number of graphene layers was determined on very small sample areas by HR-XTEM and, with high statistics and on several sample positions, by measuring the depth of selectively etched trenches in FLG by t-AFM. Both the density of wrinkles and the number of graphene layers are found to increase almost linearly as a function of the growth temperature in the considered temperature range.

Study of the Effects of Growth Rate, Miscut Direction and Postgrowth Argon Annealing on the Surface Morphology of Homoepitaxially Grown 4H Silicon Carbide Films

we study the surface morphology of homoepitaxially grown 4H silicon carbide in terms of growth rate, miscut direction of the substrate and post growth argon thermal annealings. All the results indicate that the final surface morphology is the result of a competition between energetic reorganization and kinetic randomness. Because in all observed conditions energetic reorganization favors surface ondulations (“step bunching”), out-of-equilibrium conditions are one of the keys to favor the reduction of the surface roughness to values below ~0.5 nm. We theoretically support these results using kinetics superlattice Monte Carlo simulations (KslMC)

Fast growth rate epitaxy by chloride precursors

In this paper the epitaxial process with chloride precursors has been described. In particular it has been shown that the growth rate can be increased to about 100 μm/h but higher growth rate can be difficult to reach due to the limited surface diffusion at the usual temperature of SiC epitaxy. This process gives several advantages because it gives the opportunity to increase the throughput and consequently to reduce the cost of epitaxy, using new reactor structures, and to reduce several kind of defects (Basal Plane Dislocations, Stacking Faults, Threading Dislocations) and to decrease the surface roughness at the same time.

4H-SiC Epitaxial Layer Grown on 150 mm Automatic Horizontal Hot Wall Reactor PE106

Preliminary results of 150mm SiC 4H 4°off have been obtained with the new 150mm automatic horizontal hot wall reactor PE1O6, using chlorinated chemistry (SiHCl3 + C2H4). A new injection system has been tested in two configurations and results will be shown in this paper. AFM surface roughness measurements and epi defect density have been reported.

Effects of the Growth Rate on the Quality of 4H Silicon Carbide Films for MOSFET Applications

In this paper we investigate the role of the growth rate (varied by changing the Si/H2 ratio and using TCS to avoid Si droplet formation) on the surface roughness (Rq), the density of single Shockley stacking faults (SSSF) and 3C-inclusions (i.e. epi-stacking faults, ESF). We find that optimized processes with higher growth rates allow to improve the films in all the considered aspects. This result, together with the reduced cost of growth processes, indicates that high growth rates should always be used to improve the overall quality of 4H-SiC homoepitaxial growths. Furthermore we analyze the connection between surface morphology and density of traps (Dit) at the SiO2/SiC interface in fabricated MOS devices finding consistent indications that higher surface roughness (step-bunched surfaces) can improve the quality of the interface by reducing the Dit value.

Epitaxial Growth on 150 mm 2° off Wafers

In this work a new epitaxial process on 6 inches has been performed on 2° off-cut substrate. This off-cut will reduce the material loss during substrate preparation from the crystal boule. The thickness and doping uniformity of the samples grown in the LPE reactor PE1O6 is extremely good and the PL map shows a low defects density. The roughness is slightly higher on 2° off-cut and the process window becomes narrower.

Local Electrical Properties of the 4H-SiC(0001)/Graphene Interface

Local current transport across graphene/4H-SiC was studied with nanometric scale lateral resolution by Scanning Current Spectroscopy on both graphene grown epitaxially on 4H-SiC(0001) (EG-SiC) and graphene exfoliated from highly oriented pyrolitic graphite and deposited on 4H-SiC(0001) (DG-SiC). The study revealed that the Schottky barrier height (SBH) of EG/4H-SiC(0001) is lowered by ~0.49eV. This is explained in terms of Fermi-level pinning above the Dirac point in EG due to the presence of positively charged states at the interface between Si face of 4H-SiC and carbon-rich buffer layer. Furthermore, Scanning Capacitance Spectroscopy based method allowed evaluating local electron mean free path (lgr) in graphene. lgr in EG-SiC was observed to be, on average, ~0.4 times that in DG-SiC and exhibited large point-to-point variations due to presence of laterally homogeneous positively charged buffer layer at the interface. However, lgr in graphene on SiC was observed to be larger than on standard SiO2 samples (DG-SiO2), which is explained by better dielectric screening of charged impurities and lower surface polar phonon scattering at the graphene/substrate interface.

Temperature Dependent Structural Evolution of Graphene Layers on 4H-SiC(0001)

In this study we examined the structural evolution of graphene grown on 8° off-axis 4H-SiC(0001) substrates at temperatures from 1600°C to 1700°C in Ar ambient. Morphological transformation of SiC substrate after annealing was examined by Tapping Mode Atomic Force Microscopy. Moreover, by etching-out graphene layers from graphitized SiC substrates in selective trenches we determined the number of graphene layers. Numbers of graphene layers were then independently confirmed by Transmission Electron Microscopy imaging.