Carmi Arad

Compressing Forwarding Tables for Datacenter Scalability

With the rise of datacenter virtualization, the number of entries in the forwarding tables of datacenter switches is expected to scale from several thousands to several millions. Unfortunately, such forwarding table sizes would not fit on-chip memory using current implementations. In this paper, we investigate the compressibility of forwarding tables. We first introduce a novel forwarding table architecture with separate encoding in each column. It is designed to keep supporting fast random accesses and fixed-width memory words. Then, we show that although finding the optimal encoding is NP-hard, we can suggest an encoding whose memory requirement per row entry is guaranteed to be within a small additive constant of the optimum. Next, we analyze the common case of two-column forwarding tables, and show that such tables can be presented as bipartite graphs. We deduce graph-theoretical bounds on the encoding size. We also introduce an algorithm for optimal conditional encoding of the second column given an encoding of the first one. In addition, we explain how our architecture can handle table updates. Last, we evaluate our suggested encoding techniques on synthetic forwarding tables as well as on real-life tables.

Compressing forwarding tables

With the rise of datacenter virtualization, the number of entries in forwarding tables is expected to scale from several thousands to several millions. Unfortunately, such forwarding table sizes can hardly be implemented today in on-chip memory. In this paper, we investigate the compressibility of forwarding tables. We first introduce a novel forwarding table architecture with separate encoding in each column. It is designed to keep supporting fast random accesses and fixed-width memory words. Then, we suggest an encoding whose memory requirement per row entry is guaranteed to be within a small additive constant of the optimum. Next, we analyze the common case of two-column forwarding tables, and show that such tables can be presented as bipartite graphs. We deduce graph-theoretical bounds on the encoding size. We also introduce an algorithm for optimal conditional encoding of the second column given an encoding of the first one. In addition, we explain how our architecture can handle table updates. Last, we evaluate our suggested encoding techniques on synthetic forwarding tables as well as on real-life tables.

SAL: Scaling data centers using Smart Address Learning

Multi-tenant data centers provide a cost-effective many-server infrastructure for hosting large-scale applications. These data centers can run multiple virtual machines (VMs) for each tenant, and potentially place any of these VMs on any of the servers. Therefore, for inter-VM communication, they also need to provide a VM resolution method that can quickly determine the server location of any VM. Unfortunately, existing methods suffer from a scalability bottleneck in the network load of the address resolution messages and/or in the size of the resolution tables. In this paper, we propose Smart Address Learning (SAL), a novel approach that expands the scalability of both the network load and the resolution table sizes, making it implementable on faster memory devices. The key property of the approach is to selectively learn the addresses in the resolution tables, by using the fact that the VMs of different tenants do not communicate. We further compare the various resolution methods and analyze the tradeoff between network load and table sizes. We also evaluate our results using real-life trace simulations. Our analysis shows that SAL can reduce both the network load and the resolution table sizes by several orders of magnitude.

Synchronized Blitz: A Lower Bound on the Forwarding Rate of Fully Meshed Traffic in Packet Switches

The precision of clock oscillators used in packet-based network devices is typically low. Thus, multiple nodes in a packet network, driven by different oscillators may transmit at slightly different port speeds, which may result in significant performance issues. In this paper, we show some of the performance issues that may be caused by clock wander. We use the well known benchmark of fully meshed traffic [RFC 2285] as a test case for analyzing the effect of clock tolerance on the performance of a switching device in a packet based network. We present a framework for analyzing the properties of clock synchronization and its effect on the forwarding rate of a switch. We then present the Synchronized Blitz, an all-to-one scenario where at any given time all incoming traffic into the switch is transmitted to a single port, and show that this scenario consumes more memory resources than any other scenario in our setting. Finally, we present a heuristic formula for a lower bound on the forwarding rate of a switch undergoing a mesh test. The lower bound computation is simple, and provides a useful tool for obtaining intuition about the performance of a device under a mesh test. We conclude by presenting simulation results that demonstrate the previous analysis.