Carsten Reuter

A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs

Finite impulse-response filters (FIR filters) are very commonly used in digital signal processing applications and traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on an FPGA, i. e., logic blocks and flip flops, and furthermore, the high routing delays, require compact implementations of the circuits. Hence, in lookup table-based FPGAs, e. g. Xilinx FPGAs, FIR-filters were implemented usually using distributed arithmetic. However, such filters can only be used where the filter coefficients are constant. In this paper, we present approaches for a more flexible FPGA implementation of FIR filters. Using pipelined multipliers which are carefully adapted to the underlying FPGA structure, our FIR filters do not require a predefinition of the filter coefficients. Combining pipelined multipliers and parallely distributed arithmetic results in different trade-offs between hardware cost and flexibility of the filters. We show that clock frequencies of up to 50 MHz are achievable using Xilinx XCAOxx — 5 FPGAs.

Heterogeneous multiprocessor scheduling and allocation using evolutionary algorithms

We propose a novel stochastic approach for the problem of multiprocessor scheduling and allocation under timing and resource constraints using an evolutionary algorithm (EA). For composite schemes of DSP algorithms a compact problem encoding has been developed with emphasis on the allocation/binding part of the problem as well as an efficient problem transformation-decoding scheme in order to avoid infeasible solutions and therefore time consuming repair mechanisms. Thus, the algorithm is able to handle even large size problems within moderate computation time. Simulation results comparing the proposed EA with optimal results provided by mixed integer linear programming (MILP) show, that the EA is suitable to achieve the same or similar results but in much less time as problem size increases.

A multi-core SoC design for advanced image and video compression

A flexible SoC architecture and its hardware implementation targeting advanced MPEG-4 video coding and region-of-interest detection (ROI) is presented. The multi-core architecture integrates three fully programmable processor cores and various interfaces onto a single chip, all tied to a 64-bit AMBA AHB bus. The processor cores are individually optimized to different computational characteristics, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The SoC is fabricated in a 0.18 /spl mu/m 6LM standard-cell technology, occupies about 82 mm/sup 2/, and operates at 145 MHz. A surveillance application example includes a MPEG-4 Simple Profile encoder with preceding ROI detection for superior compression results in full TV resolution.

The video and image processing emulation system VIPES

We present a real time emulation system for complete video processing schemes. Our emulation system is based on a commercial FPGA emulator and related software. To meet real time constraints, we have extended this emulation environment by dedicated video interfaces, efficient flexible FPGA macros, and a modified design flow. The feasibility of this methodology is shown for a two dimensional discrete cosine transform, resulting in a reduction of approximately 58% in terms of FPGA resources. The emulation frequency improves by 33%. Furthermore, by emulating different coefficient word widths and subjective evaluation of image quality, it could be shown that a word width of 10 bits is sufficient for our design.

Alternative approaches implementing high-performance FIR filters on lookup table-based FPGAs : A comparison

Finite impulse response filters (FIR filters) are very commonly used in digital signal processing (DSP) applications and are traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on FPGA, i.e., logic blocks and flip flops, and furthermore, the high routing delays, requires compact implementations of the circuits. Three approaches for implementation of high-performance symmetric FIR filters on lookup table-based FPGAs will be considered in this paper. Fully parallel distributed arithmetic, table lookup multiplication, and conventional hardware multiplication. Implementation results will be illustrated by an 8 taps 8 bits symmetric FIR filter, and comparative considerations of the above approaches invoked for Xilinx FPGAs will be also shown.

Architecture Concepts for Multimedia Signal Processing

Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It will be shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts—reconfigurable computing, simultaneous multithreading, and associative controlling—are presented, and their potential to increase further the performance on future multimedia applications is investigated.

Performance Estimation of Streaming Media Applications for Reconfigurable Platforms

A methodology for performance estimation of streaming media applications for different platforms is presented. The methodology derives a complexity profile for an application as a platform-independent metric, and enables performance estimation on potential platforms by correlating the complexity profile with platform-specific data. By example of an MPEG-4 Advanced Simple Profile (ASP) video decoder, performance estimation results are presented. As one particular benefit, the approach can be employed to explore what hardware functions are most suited for the implementation on reconfigurable architectures.

Benefits of macro-based multi-FPGA partitioning for video processing applications

Large rapid-prototyping systems comprising several FPGAs become more and more the tool at hand to verify complete hardware systems at an early stage of development for first time success. Although hardware capability is growing rapidly the appropriate software tools are lacking in mapping performance and quality. It is especially difficult to meet certain real-time constraints when a design is distributed among several FPGAs. We propose a macro-based partitioning methodology that significantly improves turnaround times and leads to very compact hardware realizations. We demonstrate the benefits of our approach for a real-time video processing application. In addition, compilation time and hardware resources could be reduced by 35% and 45%, respectively.

The Effect of FPGA Granularity on Video Codec Implementations

This paper presents an investigation of LUT-based FPGAs regarding their suitability for a particular application area using circuits which can be described in a typical HDL like Verilog or VHDL, not only synthetic benchmarks. The H.263 video codec has been chosen as benchmark example. In order to compare different FPGA architectures, a generic FPGA model and architecture independent modelling software are used. It is shown that coarse grain FPGAs give better area-speed trade-offs for large circuits whereas more fine grain devices are better suited for smaller designs.

A Mapping Methodology for Code Trees onto LUT-Based FPGAs

One important algorithm for data compression is the variable length coding that often utilizes large code tables.Despite the progress modern FPGAs made, concerning the available logic resources, an efficient mapping of those tables is still a challenging task. In this paper, we describe an efficient mapping methodology for code trees onto LUT-based FPGAs. Due to an adaptation to the LUTs number of inputs, for large code tables a reduction of up to 40% of logic blocks is achievable compared with a conventional gate-based implementation.