Carthik A. Sharma

Progress in autonomous fault recovery of field programmable gate arrays

The capabilities of current fault-handling techniques for Field Programmable Gate Arrays (FPGAs) develop a descriptive classification ranging from simple passive techniques to robust dynamic methods. Fault-handling methods not requiring modification of the FPGA device architecture or user intervention to recover from faults are examined and evaluated against overhead-based and sustainability-based performance metrics such as additional resource requirements, throughput reduction, fault capacity, and fault coverage. This classification alongside these performance metrics forms a standard for confident comparisons.

Consensus-Based evaluation for fault isolation and on-line evolutionary regeneration

While the fault repair capability of Evolvable Hardware (EH) approaches have been previously demonstrated, further improvements to fault handling capability can be achieved by exploiting population diversity during all phases of the fault handling process. A new paradigm for online EH regeneration using Genetic Algorithms (GAs) called Consensus Based Evaluation (CBE) is developed where the performance of individuals is assessed based on broad consensus of the population instead of a conventional fitness function. Adoption of CBE enables information contained in the population to not only enrich the evolutionary process, but also support fault detection and isolation. On-line regeneration of functionality is achieved without additional test vectors by using the results of competitions between individuals in the population. Relative fitness measures support adaptation of the fitness evaluation procedure to support graceful degredation even in the presence of unpredictable changes in the operational environment, inputs, or the FPGA application. Application of CBE to FPGA-based multipliers demonstrates 100% isolation of randomly injected stuckat faults and evolution of a complete regeneration within 135 repair iterations while precluding the propagation of any discrepant output. The throughput of the system is maintained at 85.35% throughout the repair process.

Autonomic fault-handling and refurbishment using throughput-driven assessment

An evolvable hardware paradigm for autonomic regeneration called Competitive Runtime Reconfiguration (CRR) is developed whereby an individuals performance is assessed using the dynamic properties of the population rather than a static fitness function. CRR employs a Sliding Evaluation Window of recent throughput data and a periodically updated Outlier Threshold which avoids the extensive downtime associated with exhaustive Genetic Algorithm (GA) based evaluation. The relative fitness measure favors graceful degradation by leveraging the behavioral diversity among the individuals in the population. Throughput-driven assessment identifies configurations whose discrepancy values violate the Outlier Threshold and are thus selected for modification using Genetic Operators. Application of CRR to FPGA-based logic circuits demonstrates the identification of configurations impacted by a set of randomly injected stuck-at faults. Furthermore, regeneration of functionality can be observed within a few hundred repair iterations. The viable throughput of the CRR system during the repair process was maintained at greater than 91.7% of the fault-free throughput rate under a number of circuit scenarios. CRR results are also compared with alternative soft computing approaches for autonomous refurbishment using the MCNC-91 benchmarks.

Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware

Autonomous repair and refurbishment of reprogrammable logic devices using genetic algorithms can improve the fault tolerance of remote mission-critical systems. The goal of increasing availability by minimizing the repair time is addressed in this paper using a CGT-pruned genetic algorithm. The proposed method utilizes resource performance information obtained using combinatorial group testing (CGT) techniques to evolve refurbished configurations in fewer generations than conventional genetic algorithms. A 3-bit times 2-bit multiplier circuit was evolved using both conventional and CGT-pruned genetic algorithms. Results show that the new approach yields completely refurbished configurations 37.6% faster than conventional genetic algorithms. In addition it is demonstrated that for the same circuit, refurbishment of partially-functional configurations is a more tractable problem than designing the configurations when using genetic algorithms as results show the former to take 80% fewer generations

A Sustainable Model for Integrating Current Topics in Machine Learning Research Into the Undergraduate Curriculum

This paper presents an integrated research and teaching model that has resulted from an NSF-funded effort to introduce results of current machine learning research into the engineering and computer science curriculum at the University of Central Florida (UCF). While in-depth exposure to current topics in machine learning has traditionally occurred at the graduate level, the model developed affords an innovative and feasible approach to expanding the depth of coverage in research topics to undergraduate students. The model has been self-sustaining as evidenced by its continued operation during the years after the NSF grants expiration, and is transferable to other institutions due to its use of modular and faculty-specific technical content. This model offers a tightly coupled teaching and research approach to introducing current topics in machine learning research to undergraduates, while also involving them in the research process itself. The approach has provided new mechanisms to increase faculty participation in undergraduate research, has exposed approximately 15 undergraduates annually to research at UCF, and has effectively prepared a number of these students for graduate study through active involvement in the research process and coauthoring of publications.

Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devices

Success has been demonstrated previously in the use of genetic algorithms (GAs) for autonomous fault-handling in field programmable gate array (FPGA) devices, yet the completeness of a given repair can be improved. This research explores extensions to voting systems to work in parallel with imperfect GA solutions for local permanent damage faults in the FPGA fabric. The benefits are evaluated by comparing performance with a GA that does not utilize voting, for triplex and 5-plex voting arrangements. Results indicate that recovery capability is significantly improved achieving complete repair by a process of synthesis from the incomplete repairs obtained by the GAs. Voting-enhanced systems are shown to increase the likelihood of finding a complete repair, with increases in speed and efficiency. The triplex and 5-plex voting schemes are able to find a complete repair after an average of 113.86 and 48.33 generations respectively in situations where standalone GAs consistently fail

Self-healing reconfigurable logic using autonomous group testing

A group-testing-based fault resolution is incorporated into SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) to provide an evolvable hardware system with self-healing and self-organizing properties. The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution. Reconfigurability of the SRAM-based FPGA is leveraged to locate faulty logic resources which are successively excluded by group testing using alternate device configurations. This simplifies the system architects role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance vs. availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an observer-controller model. The proposed group testing method operates on the output response produced for real-time operational inputs, which eliminates the need for dedicated test vectors. The proposed system was demonstrated using a Data Encryption Standard (DES) core on 4-input and 6-input LUT-based Xilinx FPGA models. With a single simulated stuck-at fault, the system identifies a completely validated replacement configuration within a few test stages. Results also include approaches for optimizing group size, resource redundancy, and availability. The approach demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.