Casey Smith

Si tunnel transistors with a novel silicided source and 46mV/dec swing

We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46mV/dec and high ION/IOFF ratio (∼108) and the experiment was successfully repeated after two months. Its superior operation is explained through simulation. For the first time convincing statistical evidence of sub-60mV/dec SS is presented. More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data.

Imaging local electronic corrugations and doped regions in graphene

Electronic structure heterogeneities are ubiquitous in two-dimensional graphene and profoundly impact the transport properties of this material. Here we show the mapping of discrete electronic domains within a single graphene sheet using scanning transmission X-ray microscopy in conjunction with ab initio density functional theory calculations. Scanning transmission X-ray microscopy imaging provides a wealth of detail regarding the extent to which the unoccupied levels of graphene are modified by corrugation, doping and adventitious impurities, as a result of synthesis and processing. Local electronic corrugations, visualized as distortions of the π*cloud, have been imaged alongside inhomogeneously doped regions characterized by distinctive spectral signatures of altered unoccupied density of states. The combination of density functional theory calculations, scanning transmission X-ray microscopy imaging, and in situ near-edge X-ray absorption fine structure spectroscopy experiments also provide resolution of a longstanding debate in the literature regarding the spectral assignments of pre-edge and interlayer states.

Band-Engineered Low PMOS V T with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.

Silicon Nanotube Field Effect Transistor with Core–Shell Gate Stacks for Enhanced High-Performance Operation and Area Scaling Benefits

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

We present the first demonstration of a III–V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III–V and Si devices can be processed side by side in the same Si fabrication line The L<inf>g</inf> = 500 nm device has a excellent drive current of ∼450 µA/µm and intrinsic transconductance of ∼1000 µS/µm indicating that III–V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-

Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric VTh, low Tinv (~1.4 nm), and high Ion (~780 ¿A/¿m) for N/PMOS without any intentional strain enhancement.

k

Longitudinal piezoresistance (pi) coefficients for n- and p-type double-gate (DG) FinFETs with sidewall channels along (110) surface and (110) channel direction are measured via wafer-bending experiments (51.4 and -37 X 10 -11 Pa-1 for n- and p-FinFETs, respectively) and are found to differ from bulk Si (110) (31.2 and -71.8 X 10 -11 Pa-1 for n- and p-Si, respectively). Compressive and tensile contact-etch-stop liners (CESLs) are fabricated on DG FinFETs and are found to induce higher channel stress than in planar MOSFETs, with 30% enhancement in the saturation current for the shortest channel-length devices in both n- and p-MOSFETs, whereas the long devices show little or no enhancement. The channel-length dependence of the enhancement suggests that stress coupling into the FinFET channels from the CESL occurs via the fin extensions and not through the gate.

/Metal Gates CMOS FinFETs for Multi-

Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using “laterally-actuated double-electrode NEMS” structures. The new device structure has several advantages over existing NEMS architectures such as being immune to impact bouncing and release vibrations (unlike a vertically-actuated NEMS) and offer higher flexibility to implement compact logic gates (unlike a single-electrode NEMS). A comprehensive analytical framework is developed to model different properties of these devices by solving the Euler-Bernoullis beam equation. The proposed model is validated using measurement data for the fabricated devices. It is shown that by ignoring the non-uniformity of the electrostatic force distribution, the existing models “underestimate” the actual value of Vpull-in and Vpull-out. Furthermore, novel energy efficient NEMS-based circuit topologies are introduced to implement compact inverter, NAND, NOR and XOR gates. For instance, the proposed XOR gate can be implemented by using only two NEMS devices compared to that of a static CMOS-based XOR gate that requires at least 10 transistors.

V_{\rm Th}

Recent experiments have demonstrated the ability to alleviate Fermi-level pinning, resulting in reduced Schottky barrier heights (SBHs) and reduced contact resistivity by inserting thin layers of dielectric at the contact interface. In this letter, FinFETs with dielectric SBH tuning layers are investigated and shown to have reduced contact resistance over the control wafer. The reduced contact resistivity results in an ≈25% increase in drive current as well as a reduction of RS/D by 100 Ω · μm. Contact chain measurement shows a 10-Ω · μm2 reduction in specific contact resistivity over the control wafer associated with a 100-meV reduction in SBH. Routes to further improvements in device performance are discussed, including key material considerations for dielectric tuning layers.

Engineering

We demonstrate for the first time that both SiGe and Ge channel with high-k/metal gate stack pMOSFETs show similar uniaxial stress enhanced drive current as Si which is expected from k.p calculations. We also demonstrate experimentally that pMOSFETs with strained quantum wells (QW) in the Si-Ge system exhibited high performance and low off-state leakage comparable to optimized gate stacks on Si. These results significantly hasten the feasibility of realizing SiGe or Ge channel pMOSFETs for 22 nm and beyond.