Cathie J. Burke

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.

Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits

The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.

A Fully Integrated Silicon-Based 40-V Thermal Ink Jet IC

A fully-integrated silicon-based thermal ink jet printhead which produces high speed, laser-quality printing at 300 spots per inch resolution is described. Monolithic integration of the 5-V logic circuitry, 13-V predriver circuitry, 40-V MOSFETs, and 192 n+ polysilicon heater elements requires multiple process and device design trade-offs. The TIJ printhead is customer replaceable and must be protected from far greater static discharges than normal VLSI circuits. Design issues and failure mechanisms of the power MOSFETs and ESD protection devices are discussed. Two-dimensional simulations which include parasitic bipolar action and lattice heating illustrate the design concepts. Electrical characteristics of the 40-V power MOSFETs and 16-kV ESD protection devices are presented.

Placement of substrate contacts to alleviate substrate noise in epi and non-epi technologies

The placement of substrate contacts in epi and non-epi technologies in order to control and reduce the substrate noise amplitude and spreading is analyzed. The choice of small or large substrate contacts or rings for each of the two major technologies are highlighted. Design guidelines for placing substrate contacts particularly appropriate to improving the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.

Power n-MOSFET design for a 40-V 192-element thermal ink jet IC

Summary form only given. A silicon-based thermal ink jet (TIJ) printhead which produces high-speed, laser-quality printing with a 300 spot per inch resolution has been designed, fabricated, and tested. The 5-V addressing logic, 13-V predriver circuitry, 40-V power MOSFET switches, and 192-drop ejectors are integrated on a single chip, and controlled by only seven external connections. The authors discuss the specific TIJ process and device design tradeoffs, especially focusing on the 40-V smart-power MOSFETs, and illustrate them with 2-D numerical modeling and experimental device data. >

A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise

A comparative study of the behavior of NMOS and CMOS digital circuits in terms of the ability to tolerate substrate noise is presented. Theoretical and simulation results are confirmed by experimental data gathered from the analysis of NMOS and CMOS test chips. It is shown that while the noise sensitivity of NMOS digital circuits is influenced by a variety of factors, the primary phenomenon responsible for the noise integrity of the CMOS digital circuits is latch-up.