Caxton C. Foster

The Inhibition of Potential Parallelism by Conditional Jumps

This note reports the results of an examination of seven programs originally written for execution on a conventional computer (CDC-3600). We postulate an infinite machine, one with an infinite memory and instruction stack, infinite registers and memory, and an infinite number of functional units. This machine wiU exectite a program in parallel at maximum speed by executing each instruction at the earliest possible moment.

Percolation of Code to Enhance Parallel Dispatching and Execution

This note investigates the increase in parallel execution rate as a function of the size of an instruction dispatch stack with lookahead hardware. Under the constraint that instructions are not dispatched until all preceding conditional branches are resolved, stack sizes as small as 2 or 4 achieve most of the parallelism that a hypothetically infinite stack would.

Counting Responders in an Associative Memory

A method of determining the number of responders to a search in an associative memory is presented. It is shown that less than one full adder per memory cell is required and that the maximum delay in establishing the count is proportional to n, where n is the log to the base 3 of the number of memory cells.

A generalization of AVL trees

A generalization of AVL trees is proposed in which imbalances up to Δ are permitted, where Δ is a small integer. An experiment is performed to compare these trees with standard AVL trees and with balanced trees on the basis of mean retrieval time, of amount of restructuring expected, and on the worst case of retrieval time. It is shown that, by permitting imbalances of up to five units, the retrieval time is increased a small amount while the amount of restructuring required is decreased by a factor of ten. A few theoretical results are derived, including the correction of an earlier paper, and are duly compared with the experimental data. Reasonably good correspondence is found. 0

Finding an extremum in a network

We propose a method for implementing “the election process” - finding an extrema of values computed in a multiprocessor network. It operates in an average time less than Log2(N), for a network of size N. It requires a single register, memory cell, or global buss into which all the processors can attempt to write, with the success of one guaranteed; and from which they may all read, in parallel. A second method is given which guarantees termination in O(Log2(MAX)) steps.

A view of computer architecture

An attempt is made to predict the developments of the next 25 years in the field of computer architecture. Standardized, inexpensive microcomputers on a single chip are predicted. These will be used extensively to provide logical functions for noncomputational devices and incidentally for the design of superscale computers.

Determination of Priority in Associative Memories

Abstract—The problem of resolving multiple responses to a search in an associative or content-addressable memory is considered. A resolver is presented whose maximum delay is proportional to the logarithm of the size of the memory.

Measures of Op-Code Utilization

The static and dynamic utilization of a set of machine op-codes is examined. Two measures of the effective use of machine instructions are discussed and applied to samples of hand-coded programs and object code.

An Unclever Time-Sharing System

This paper describes the internal structure of a time-sharing system in some detail. This system is dedicated to providing remote access, and has a simple file structure. It is intended for use in a university type environment where there are many short jobs that will profit from one- or two-second turnaround. Despite its simplicity, this system can serve as a useful introduction to the problems encountered by the designers of any time-sharing system. Included are a discussion of the command language, the hardware organization toward which the design is oriented, the general internal organization, the command sequences, the CPU scheduler, handling of interrupts, the assignment of core space, execution and control of the users program, backup storage management, and the handling of errors.

An Algorithm for Intercell Communication in a Tesselated Automaton

An algorithm is presented which permits any arbitrary subset of the cells of a content addressable tresselated automaton (CATA) to communicate with any other arbitrary subset.