Cecilia Gimeno

CMOS transimpedance amplifier with controllable gain for RF overlay

In this paper, a fully-differential transimpedance amplifier (TIA) with controllable transimpedance for use in RF overlay downstream communication systems is presented. It consists of a shunt-shunt feedback transimpedance amplifier with transimpedance and open loop gain control. The transimpedance amplifier is intended for 47 MHz to 870 MHz subcarrier multiplexed RF signals with a 18 dBΩ transimpedance gain control range. The TIA, designed in a CMOS 180 nm technology, dissipates 27 mW from a supply voltage of 1.8 V. The input-referred noise current is lower than 6 pA/√Hz to allow an optical input power from -6 to +2 dBm.

A fully-differential adaptive equalizer using the spectrum-balancing technique

A low-voltage high-speed CMOS fully-differential adaptive equalizer based on the spectrum-balancing technique is presented in this paper. It was designed to compensate the strong attenuation of the transmitted signal due to fiber losses. The proposed equalizer, formed by a line equalizer and an adaptation loop, targets 2.5 Gb/s transmission for a simple NRZ modulation through a 50-m SI-POF. It was designed in a 0.18-μm standard CMOS process, fed with 1V and has a power consumption below 17.3 mW.

New Multilevel Bang-Bang Phase Detector

Equivalent time oscilloscopes are widely used as an alternative to real-time oscilloscopes when high timing resolution is needed. For their correct operation, they need the trigger signal to be accurately aligned to the incoming data, which is achieved by the use of a clock and data recovery circuit (CDR). In this paper, a new multilevel bang-bang phase detector (BBPD) for CDRs is presented; the proposed phase detection scheme disregards samples taken close to the data transitions for the calculation of the phase difference between the inputs, thus eliminating metastability, one of the main issues hindering the performance of BBPDs.

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/Hz at 50 kHz, which corresponds to 100 μg/Hz.

CMOS receiver with equalizer and CDR for short-reach optical communications

This paper presents an optical receiver for short reach applications through low-cost plastic optical fiber. The limited bandwidth caused by the fiber and the external photodiode is compensated by a new adaptive equalizer based on the spectrum balancing technique. A clock and data recovery circuit is included that minimizes jitter and metastability using a new multi-level bang-bang architecture. The prototype, implemented in a standard 0.18-μm CMOS process, achieves 1.25 Gb/s with a power under 110 mW at only 1 V.

Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs

This work investigates, for the first time to our best knowledge, non-linearities in Fully-depleted Silicon-on-Insulator (FDSOI) MOSFETs and compares them with bulk counterparts. 1^st, 2^nd and 3^rd order derivatives of current-voltage I–V characteristics, followed by Harmonic Distortions of 2^nd and 3^rd order (HD<inf>2</inf> and HD<inf>3</inf>) were extracted based on DC measurements and simulations. Design window (i.e. bias and current conditions) with strongly reduced non-linearity in FDSOI device with respect to the bulk counterpart was identified and reasons of this reduction are discussed. Application of the back-gate bias in FDSOI MOSFET was shown to allow for further improvement of non-linearity.

Continuous-time equalizer for CMOS integrated photodiodes

Fully integrated optoelectronic interfaces in CMOS technology are a very interesting option for optical smart sensors because they are a cost-effective and compact solution. However, CMOS standard n-well/p-bulk differential photodiodes (DPDs) are the bottleneck in this field due to their inherent limited bandwidth which falls below 10MHz in 65nm CMOS. This work presents a new equalization approach to enhance the bandwidth of CMOS integrated DPDs used in optical sensors. It is designed based on a split-path topology in which the gain and the boost are completely decoupled and can be externally adjusted by means of independent control voltages. This feature, particularly helpful for calibration, is not present in conventional equalizers based on the degenerated differential pair. The proposed equalization technique has been simulated in a 65nm process, where it has been able to increase the bandwidth of the DPD from their inherent 10MHz up to 3GHz with a single supply voltage of only 1.2V.

An Adaptive Bitrate Clock and Data Recovery Circuit for Communication Signal Analyzers

Many measurement instruments require an external timing reference to perform an accurate measurement. In equivalent-time oscilloscopes, for example, a trigger signal properly aligned to the data is essential, since they base their operation on a very accurate delay of the trigger, which is obtained by a clock and data recovery (CDR) circuit. In this paper, an adaptive bitrate CDR circuit for instrumentation applications is presented. It is designed in a standard 0.18-μm CMOS technology with a single supply voltage of 1.8 V and operates from 312.5 Mb/s to 2.5 Gb/s with a maximum power consumption of 140 mW and occupies an area of 1.5 mm × 0.6 mm.

A 1-V CMOS double loop continuous-time adaptive equalizer for short-haul optical networks

This paper presents a low-voltage CMOS continuous-time adaptive equalizer for short-haul gigabit optical communications. It was designed to compensate the attenuation of a 1.25 Gb/s signal with a simple NRZ modulation, transmitted through a 50-m length 1-mm core step-index plastic optical fiber (SI-POF). The structure includes two adaptation loops to compensate the possible variations in level and spectrum of the input signal. The proposed system was designed in a cost-effective 0.18-μm CMOS process. The system is fed with 1 V and has a total power consumption of 29.3 mW.

Design considerations for loop filters in continuous-time adaptive equalizers

Continuous-time adaptive equalization at the receiver of high-speed serial communications systems is a commonly used solution to overcome the degradation of the signal caused by channel bandwidth limitations. The design of an adaptive equalizer is carried out either in the time domain using a comparator or in the frequency domain using the spectrum balancing technique. This work shows that these two approaches are equivalent and can be understood in the frequency domain only. Furthermore, it uses a unified theoretical description to formulate design criteria for the practical implementation of continuous-time adaptive equalizers.