Cédric Lorand

Total delay compensation in LAN control systems and implications for scheduling

In the first part of this paper it is shown that long access delays are not necessarily detrimental to the stability of local area network embedded control systems. In the second part we show that (under some mild conditions on the control system) scheduling in the return path is not needed. This is a consequence of the fact that for local area networks the access delays can be exactly determined and completely eliminated from the system representation.

On Synchronization Errors in Networked Feedback Systems

This paper addresses the problem of synchronization errors and their effects on feedback loops that are closed over communication networks. It is assumed that the feedback loop consists of two discrete-time systems, the clock frequency ratio of which has a special rational form, and is close to one. A Toeplitz matrix approach is taken to model the input/output relationship of the arising feedback systems. Based on this representation, the effect of synchronization errors on stability of the feedback systems is analyzed. It is shown that stability of the synchronized feedback loop can not guarantee stability of the loop in the presence of synchronization errors. Necessary and sufficient stability conditions are derived

Clock Synchronization Errors in Circuits: Models, Stability and Fault Detection

This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fault detection and identification methods for this type of system are provided, by using a state-space approach to asynchronously switching systems

Distributed discrete-time systems with synchronization errors: models and stability

The problem addressed in this brief originates from the use of nonidentical clocks in distributed systems, i.e., clocks with slightly different frequencies. At first, we introduce an event driven state space model for asynchronous system equations. Then, we derive necessary and sufficient conditions for stability and show that unlike in the case of synchronous operations, the slightest mismatch in clock frequencies can destabilize the system, even if the synchronously operating system has a large margin of stability. New light is shed on the importance of the degree of synchronization and its connection to stability.

Stability of first order discrete time systems with time-variant communication delays in the feedback path

This paper addresses the problem of stability in 1st order systems with time-variant communication delays in the feedback path. Sets of necessary and sets of sufficient conditions are obtained and resulting stability regions are shown.

Stability analysis of closed-loop discrete-time systems with clock frequency drifts

The effect of a slight mismatch in the clock frequencies of a distributed feedback system is investigated. The stability behavior is analyzed and necessary and sufficient conditions for BIBO stability are derived. It is shown that stability of the synchronously operating feedback system can be lost for even extremely small frequency drifts, i.e. the synchronously operating system has no stability robustness with respect to clock frequency drifts.

Stabilizing mantissa rates in feedback systems with floating-point quantization

This paper studies stabilizing data rates for unstable plants with limited data rates in the state feedback path. The effects of limited data rates and time-variant delays are modeled for the case of floating point number representation. Bounds for stabilizing mantissa rates are obtained and some interesting special cases are highlighted. The first order case is discussed in detail and a number of new results for stabilizing data rates are shown.

Clock synchronization errors in circuits: models, stability and fault detection

This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fault detection and identification methods for this type of system are provided, by using a state-space approach to asynchronously switching systems.

Stability robustness of interconnected discrete time systems with synchronization errors

This paper addresses the effects of synchronization errors in two interconnected discrete time systems represented in state space with small clock frequency mismatches. An event based discrete time index is used to capture the dynamics of the arising system. In a second step, the stability of the overall system is analyzed and compared to the stability of both the perfectly synchronized system (with identical clock signals) and the synchronized system with a non-zero phase difference between the two clock signals.