Cesar Pedraza

Cluster architecture based on low cost reconfigurable hardware

The SMILE project accelerates scientific and industrial applications by means of a cluster of low-cost FPGA boards. With this approach the intensive calculation tasks are accelerated using the FPGA logic, while the communication patterns of the applications remains unchanged by using a Message Passing Library over Linux. This paper explains the cluster architecture: the SMILE nodes and the developed high-speed communication network for the FPGA RocketIO interfaces. A SystemC model developed to simulate the cluster is also detailed. In order to show the potential of the SMILE proposal a Content-Based Information Retrieval parallel application has been developed and compared with a HP cluster architecture in terms of response time andpower consumption.

Genetic Algorithm for Boolean minimization in an FPGA cluster

Evolutionary algorithms are an alternative option to the Boolean synthesis due to that they allow one to create hardware structures that would not be able to be obtained with other techniques. This paper shows a parallel genetic programming (PGP) Boolean synthesis implementation based on a cluster of FPGAs that takes full advantage of parallel programming and hardware/software co-design techniques. The performance of our cluster of FPGAs implementation has been compared with an HPC implementation. The experimental results have shown an excellent behavior in terms of speed up (up to ×500) and in terms of solving the scalability problems of this algorithms present in previous works.

Exploring FPGA Capabilities for Building Symmetric Multiprocessor Systems

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.

A Self-Reconfigurable Multimedia Player on FPGA

With the hype of multimedia devices, many different audio and video formats have appeared in recent years. The sales of portable multimedia players like Apples ipod have also experiment and incredible growth. These devices are usually based on general purpose microprocessors and, when a new audio or video format appears, a software upgrade is needed or, in the worst case, the new format will not be supported by the player. This work presents a novel implementation where an FPGA based multimedia player makes use of the self-reconfiguration capabilities of modern FPGA families in order to support new multimedia formats. When the player needs to play a song with a non-supported format it securely downloads the required hardware from Internet and reprograms the FPGA with the new codec

Self-reconfigurable secure file system for embedded Linux

With the growth of the portable electronic devices market, not only the protection of the data for the users but also the security of the designs themselves has grown significantly in importance. A solution is presented where a Linux kernel running on a PowerPC processor included in the Virtex-II Pro FPGA family is upgraded to support hardware acceleration on the ciphering tasks. In this way all the programs running on the PPC that make use of the Linux CryptoAPI can be accelerated by hardware in a transparent way without having the programmer to rewrite the applications. To provide more flexibility, the FPGAs self-reconfiguration capability can be used to reprogram any cryptographic algorithm demanded by the Linux CryptoAPI by just including a new software driver for the operating system, thus allowing the internal configuration access port (ICAP) of the FPGA to manage any cryptographic coprocessor at any time. The approach is validated on a real application using the Linux CryptoAPI: a ciphered file system that stores the system data in a secured way.

Hierarchical NoC-based security for MP-SoC dynamic protection

MPSoCs are able to support multiple applications on the same chip. This flexibility offered by the MPSoC also represents a vulnerability, turning the MPSoC security specially challenging. The goal of the designers is to provide MPSoC protection that meets the performance and security requirements of all the applications. The Network-on-chip (NoC) interconnection structure can be used to efficiently overcome the present MPSoC vulnerabilities. In this paper, we present the implementation of a hierarchical security NoC-based architecture to detect and prevent a wide range of MPSoC attacks. We integrate agile and dynamic security firewalls into the NoC in order to detect attacks based on different security rules. It uses the QoSS (Quality of Security Service) concept. It takes into account the tradeoff between security and performance. We evaluate the effectiveness of our approach over several MPSoCs attack scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications.

QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs

Three dimension Multi processors System-on-Chip (3D-MPSoCs) hold promises to allow the development of compact and efficient devices. They support many applications on the same die, able of being mapped dynamically during the execution time. Each application may have different communication requirements. Quality-of-Service (QoS) can be implemented at the communication structure (CS) to support the communication requirements of the dynamic 3D-MPSoC. Our work proposes QoS 3D-HoC, a new 3D-CS that implements the QoS. We evaluate the performance of our architecture over several 3D-MPSoC synthetic and real traffic scenarios and estimate their impact overall CS performance. We compare our architecture against the previous 3D-CS with and without QoS and show that our approach meets the communication requirements while reducing the latency and power up to 87% and 39%, respectively when compared to single 3D-NoC.

Symmetric Multiprocessor Systems on FPGA

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors, increasing the range of applications that can be implemented on an FPGA. In this paper we propose a symmetric multiprocessor architecture using the Microblace soft-core processor, and the operating system support needed for running multithreaded applications. Four systems with different shared memory configurations have been implemented on FPGA and tested with parallel applications to show its performance.

Parallel Implementation of the Shortest Path Algorithm on FPGA

An implementation of a parallel version of the shortest path algorithm on a Virtex-II Pro FPGA device that computes the minimal distance in a graph in a more efficiently way than the classical algorithms is presented The paper shows how the hardware/software codesign process is applied in order to design the system using a PowerPC processor running Linux on a XUP Virtex-II Pro development board. The coprocessors hardware architecture is fully described as well as the software running in Linux that is in charge of transferring data between the host computer, the PPC and the application-specific coprocessor. The synthesis results are presented as well as a comparative study of speedups for the parallel and the sequential implementation of the algorithm, showing a good improvement from the presented version against a software version running in a PC.

Low Cost High Performance Reconfigurable Computing

High Performance Reconfigurable Computing (HPRC) has emerged as an alternative way to accelerate applications using FPGAs. Although these HPRC systems have a performance comparable to standard supercomputers and at a much lower cost, HPRC systems are still not affordable for many institutions. We present a low-cost HPRC system built on standard FPGA boards with an architecture that can execute many scientific applications faster than in Graphical Processor Units and traditional supercomputers. The system is made up of 32 low-cost FPGA boards and a custom-made high-speed network interface using RocketIO interfaces. We have designed a SystemC methodology and CAD framework that allow the designer to simulate any MPI scientific application before generating the final implementation files. The software runs on the PowerPC processor embedded in the FPGA on a light ad-hoc implementation of MPI, and the hardware is automatically translated from SystemC to Verilog, and connected to the PowerPC. This makes the SMILE HPRC system fully compatible with any existing MPI application. The proof of the concept of the SMILE HPRC has been exhaustively tested with two complex and demanding applications: the Monte Carlo financial simulation and the Boolean Synthesis using Genetic Algorithms. The results show a remarkable performance, reasonable costs, small power consumption, no need of cooling systems, small physical space requirements, system scalability and software portability.