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Chang-Sheng Chen

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Publication

Featured researches published by Chang-Sheng Chen.

Archive | 2000

Vertical structure for semiconductor wafer-level chip scale packages

Y. Mohammed Kasem; Yueh-Se Ho; Lee Shawn Luo; Chang-Sheng Chen; Eddy Tjhia; Bosco Lan; Jacek Korec; Anup Bhalla

Archive | 2004

Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys

Mohammed Kasem; King Owyang; Frank Kuo; Serge Robert Jaunay; Sen Mao; Oscar Ou; Peter Wang; Chang-Sheng Chen

Archive | 2001

Vertical structure and process for semiconductor wafer-level chip scale packages

Y. Mohammed Kasem; Yueh-Se Ho; Shawn Luo Lee; Chang-Sheng Chen; Eddy Tjhia; Bosco Lan; Jacek Korec; Anup Bhalla

Archive | 2012

SEMICONDUCTOR PACKAGE INCLUDING DIE INTERPOSED BETWEEN CUP-SHAPED LEAD FRAME HAVING MESAS AND VALLEYS

Mohammed Kasem; Frank Kuo; Robert Jaunay Serge; Mao Sen; Oscar Ou; Peter Wang; Chang-Sheng Chen

Archive | 2005

A semiconductor device comprising a chip which is arranged between a cup-shaped printed circuit board and a circuit board having mesas and valleys, and methods for its preparation

Mohammed Kasem; Frank Kuo; Serge Robert Jaunay; Sen Mao; Oscar Ou; Peter Wang; Chang-Sheng Chen

Archive | 2005

Halbleiterbauelement mit einem Chip, der zwischen einer becherförmigen Leiterplatte und einer Leiterplatte mit Mesas und Tälern angeordnet ist, und Verfahren zur dessen Herstellung A semiconductor device comprising a chip which is arranged between a cup-shaped printed circuit board and a circuit board having mesas and valleys, and process for its preparation

Mohammed Kasem; Frank Kuo; Serge Robert Jaunay; Sen Mao; Oscar Ou; Peter Wang; Chang-Sheng Chen

Archive | 2005

Boitier a semi-conducteurs comprenant un de interpose entre un reseau de conducteurs se presentant sous forme d'une cuillere et un reseau de conducteurs comprenant des mesas et des creux

Mohammed Kasem; Frank Kuo; Serge Robert Jaunay; Sen Mao; Oscar Ou; Peter Wang; Chang-Sheng Chen

Archive | 2001

Vertical structure and process for the production of wafer-level semiconductor packaging arrangements in chip size

Mohammed Y Kasem; Yueh-Se Ho; Shawn Luo Lee; Chang-Sheng Chen; Eddy Tjhia; Bosco Lan; Jacek Korec; Anup Bhalla

Archive | 2001

Process for semiconductor wafer-level chip scale packages

Anup Bhalla; Chang-Sheng Chen; Yueh-Se Ho; Mohammed Y Kasem; Jacek Korec; Bosco Lan; Shawn Luo Lee; Eddy Tjhia

Archive | 2001

Vertikale struktur und verfahren zur herstellung von wafer-ebene halbleiterpackungsanordnungen in chipgrösse Vertical structure and process for production of wafer-level semiconductor packaging arrangements in chip size

Mohammed Y Kasem; Yueh-Se Ho; Shawn Luo Lee; Chang-Sheng Chen; Eddy Tjhia; Bosco Lan; Jacek Korec; Anup Bhalla

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